9 Commits

Author SHA1 Message Date
Damien Lespiau
f0365d40b4 assembler: Don't use GL types
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \
       -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \
       -e 's/GLshort/int16_t/g' assembler/*.[ch]

Drop the GL types here, they don't bring anything to the table. For
instance, GLuint has no guarantee to be 32 bits, so it does not make too
much sense to use it in structure describing hardware tables and
opcodes.

Of course, some bikeshedding can be applied to use uin32_t instead, I
figured that some of the GLuint are used without size constraints, so
a sed with uint32_t did not seem the right thing to do. On top of that
initial sed, one bothered enough could change the structures with size
constraints to actually use uint32_t.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04 15:54:42 +00:00
Damien Lespiau
2d8b92a24b assembler: Remove trailing white space
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04 15:54:42 +00:00
Damien Lespiau
67f3f949bf assembler: Add support for D and UD in 3-src instructions
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04 15:54:41 +00:00
Damien Lespiau
a2a6583518 assembler: Expose setters for 3src operands
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04 15:54:41 +00:00
Damien Lespiau
d3a2a678d5 assembler: Implement register-indirect addressing mode in brw_set_src1()
The assembler allows people to do that and that's something available
since Crestline.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04 15:54:40 +00:00
Damien Lespiau
e7cca1a3ca assembler: Use brw_set_src0()
Unfortunately, it's all a walk in the park. Both, internal code in the
assembler and external shaders (libva) generate registers that trigger
assertions in brw_eu_emit.c's brw_validate().

To fix all that I took the option to be able to emit warning with the -W
flag but still make the assembler generate the same opcodes.

We can fix all this, but it requires validation, something that I cannot
do right now.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04 15:54:40 +00:00
Damien Lespiau
103edccd9b assembler: Fix comparisons between reg.type and Architecture registers
Of course the assertion is there to make sure GRF and MRF have a reg.nr
< 128. To exclude ARF registers, reg.file has be checked, not reg.type
(channel type). Most likely a typo never caught.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04 15:54:39 +00:00
Damien Lespiau
6e83eb66b1 assembler: ExecSize can be as big as 32 channels
See the IVB PRM, vol4 part3 5.2.3.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04 15:54:39 +00:00
Damien Lespiau
042e9353e9 assembler: Import brw_eu_emit.c
Finally importing the meaty brw_eu_emit.c code that emit instructions.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04 15:54:37 +00:00