4 Commits

Author SHA1 Message Date
Chris Wilson
95426dc206 tests/gem_(cpu|gtt)_concurrent_blit: Enable signals
In order to exercise the bug behind:

commit 22fd5ca947b58901927d100d2b1aa0f1672b3435
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Fri Jun 28 16:54:08 2013 +0100

    drm/i915: Only clear write-domains after a successful wait-seqno

we need to check for concurrent access with the potential to be
interrupted by a signal. The framework for doing so is already in place,
so just enable it and repeat the tests for longer to give better chance
of being interrupted at just the wrong moment.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2013-06-29 16:37:20 +01:00
Daniel Vetter
a2778575d5 tests/gem_gtt_concurrent_blit: convert to subtest infrastructure
Same treatment as for gem_cpu_concurrent_blit.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-28 12:35:03 +01:00
Daniel Vetter
d9fb72e266 tests: improve concurrent blit tests
By adding another testcase that follows up with a gpu read. This
checks whether the kernel properly tracks the pending write and
doesn't lose it (or sync up to the wrong seqno).

For some odd reason only the cpu mmap variant blows up, the gtt one
works here. I need to look into that some more.

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-13 10:35:11 +02:00
Daniel Vetter
8f6ebd4ac0 tests: add gem_gtt_concurrent_blit
Same test as Chris Wilson's gem_cpu_concurrent_blit, but for
gtt mmaps.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-04-11 15:28:26 +02:00