The MOCS registers were added in Gen9 and define the caching policy.
The registers are split into two sets. The first set controls the
EDRAM policy and have a set for each engine, the second set controls
the L3 policy. The two sets use the same index.
The RCS registers and the L3CC registers are stored in the RCS context.
The test checks that the registers are correct by checking the values by
directly reading them via MMIO, then again it tests them by reading them
from within a batch buffer. RCS engine is tested last as it programs the
registers via a batch buffer and this will invalidate the test for
workloads that don't use the render ring or don't run a render batch
first.
v2: Reorganised the structure.
Added more tests. (Chris Wilson)
v3: Fixed a few bugs. (Chris Wilson)
v4: More Tidy-ups. (Chris Wilson)
SKL does does not have a snoop bit. (Peter Antoine)
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Remember that we allocate and use twice as many buffers as specified (we
have a num_buffers array of src and dst) and so adjust the computation
such that the combined allocation matches the target.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
When forking, the entire VM is cloned including the VMA backed by GEM
objects from the libdrm buffer cache. This is not only slow, but can also
cause the system to exceed the maximum number of VMA and premature test
failure.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
My BSW takes ~12 seconds to go back to idle after high load, so the
current 10s timeouts are too short. Bump them up to 15s.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
CHV pipe B has some extra features (programmable sprite CSC,
primary plane windowing, primary plane scaler, fancier blending).
Add all the relevant registers to the "quickdump" register list.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
i915 does not yet support the atomic modesetting interface by default;
at the moment it must be turned on explicitly via an
'i915.nuclear_pageflip' kernel command line option. We should skip
(rather than fail) this IGT test when running on kernels that don't
advertise support for atomic modesetting.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93014
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
This fixes potential crashes when the framebuffer is unset from a
given plane.
v2: s/with/within/ typo in header
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Marius Vlad <marius.c.vlad@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
Actually use the builtin register spec on gen4. Makes intel_reg dump
actually do something on gen4.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Hitting oom from userptr because we had N threads all consuming all of
memory, wasn't the intention but the bugs it found were useful!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Just a set of scripts to integrate these benchmarks with ezbench. They
need to be revised to plugin into latest version of ezbench.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
The timer is tied to the creator thread, i.e. it is not inheritable
across fork() or clone()/pthread_create(). Using it thus causes an
assertion failure in the test after the one that aborts (and so on until
we perform an interruptible test correctly) - one mistake snowballs. We
can stop the snowball by doing an initial check and diverting back to
drmIoctl().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Since the last errno doesn't correspond with the signal, reporting it
when we detect the GPU hang is confusing.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
With lockdep enabled, the driver overhead is enormous and we need to
slow down the GPU to compenstate (otherwise the GPU is already idle when
we expect busyness). So do more work per batch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
A little more inelegant as we can't control the delay very well, but it
should prove more vesatile and broaden the test coverge (and still be
quick enough for basic).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
The selftest is already before the suspend/hibernate tests, but to be
clear also run it first (it only takes a millisecond) by itself.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
On bdw, the render ring becomes full and limits dispatch across all rings.
Adjust the expected latency to take this into account.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Execute the batch concurrently on all rings and then wait (as opposed to
executing a different batch on each engine).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
For sync, it really is just the average latency across all rings, but
for continuous we can expect to see the effect of concurrent dispatch
across rings. Hopefully.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
When we aren't deliberately injecting hangs, we don't expect to see any
GPU hang. Detect them and fail early.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
If we listen to the uevents from the kernel, we can detect when the GPU
hangs. This requires us to fork a helper process to do so and send a
signal back to the parent.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
"Leak" the objects from each test until each process has allocated
enough objects to consume all of RAM.
Doing so from each process not only ensures we do stress the allocation
paths, but also obsoletes the separate purgeable helper.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This test exercise purely to exercise the shrinker under some common
stress (i.e. paths leading to i915_gem_object_get_pages()). We try to
fill the entirely of memory split amongst many processes so that each
individual process only consumes a small fraction of RAM (less than the
mappable aperture) and a single process should not be individually
blamed.
Based on an idea to have a seperate set of memory stress tests by Piotr
Luc.
Cc: Piotr Luc <piotr.luc@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
The GAMMA_LUT/DEGAMMA_LUT/CTM properties must be updated when the
legacy ioctl is triggered to ensure the new properties do not impact
older userspace code.
v2: Add checks verifying the content of CTM & DEGAMMA_LUT properties
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This test enables testing of :
* degamma LUTs
* csc matrix
* gamma LUTs
* legacy gamma LUTs
v2: turn assert into require to skip on platform not supporting color
management
v3: add invalid blob ids tests
v4: Try to match CRC results against several values around the
expected result for platforms with odd LUT items
v5: Fix running tests with multiple screens
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This is a helper to draw a gradient between 2 colors.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
v2: Rename CTM_MATRIX property to CTM
v3: Add support for atomic commits
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
