mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-07 07:56:17 +00:00
Converted a display debug script for use by designers
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Ben Widawsky
parent
ea944a9faf
commit
d400551144
17
scripts/convert_itp.py
Executable file
17
scripts/convert_itp.py
Executable file
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#!/usr/bin/env python3
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#this script helps to convert internal debugger scripts given to us into our tools
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import sys
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import fileinput
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def replace_with_dict(text, dicto):
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for key, val in dicto.items():
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text = text.replace(key, val)
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return text
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for lines in fileinput.input([sys.argv[1]], inplace=True):
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lines = lines.strip()
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if lines == '': continue # strip empty lines
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replace_dict = {'dword(' : '../tools/intel_reg_read ', 'MMADDR + ' : '', '//' : '#', ')p;' : '', ')p ' : ' -c '}
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print(replace_with_dict(lines, replace_dict))
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172
scripts/display_debug.sh
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172
scripts/display_debug.sh
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#!/bin/bash
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# FBC_CFB_BASE 0x43200
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../tools/intel_reg_read 0x43200
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# FBC_CTL 0x43208
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../tools/intel_reg_read 0x43208
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# ERR_INT 0x44040
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../tools/intel_reg_read 0x44040
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# DE_RRMR 0x44050
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../tools/intel_reg_read 0x44050
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# ARB_CTL 0x45000
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../tools/intel_reg_read 0x45000
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# ARB_CTL2 0x45004
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../tools/intel_reg_read 0x45004
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# MSG_CTL 0x45010
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../tools/intel_reg_read 0x45010
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# Watermarks
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../tools/intel_reg_read 0x45100
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../tools/intel_reg_read 0x45104
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../tools/intel_reg_read 0x45200
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../tools/intel_reg_read 0x45108
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../tools/intel_reg_read 0x4510C
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../tools/intel_reg_read 0x45110
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../tools/intel_reg_read 0x45120
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../tools/intel_reg_read 0x45124
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../tools/intel_reg_read 0x45128
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# Pipe A timing 0x60000-0x6004C
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../tools/intel_reg_read 0x60000 -c 0x13;
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# Pipe B timing 0x61000-0x6104C
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../tools/intel_reg_read 0x61000 -c 0x13;
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# Pipe C timing 0x62000-0x6204C
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../tools/intel_reg_read 0x62000 -c 0x13;
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# FDI A 0x60100
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# FDI B 0x61100
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# FDI C 0x62100
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# EDP 0x64000
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../tools/intel_reg_read 0x60100
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../tools/intel_reg_read 0x61100
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../tools/intel_reg_read 0x62100
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../tools/intel_reg_read 0x64000
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# Panel fitter A window size 0x68074
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# Panel fitter A control 0x68080
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../tools/intel_reg_read 0x68074
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../tools/intel_reg_read 0x68080
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# Panel fitter B window size 0x68874
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# Panel fitter B control 0x68880
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../tools/intel_reg_read 0x68874
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../tools/intel_reg_read 0x68880
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# Panel fitter C window size 0x69074
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# Panel fitter C control 0x69080
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../tools/intel_reg_read 0x69074
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../tools/intel_reg_read 0x69080
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# Pipe A config 0x70008
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# Pipe B config 0x71008
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# Pipe C config 0x72008
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../tools/intel_reg_read 0x70008
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../tools/intel_reg_read 0x71008
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../tools/intel_reg_read 0x72008
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# Cursor A control 0x70080
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# Cursor B control 0x71080
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# Cursor C control 0x72080
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../tools/intel_reg_read 0x70080
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../tools/intel_reg_read 0x71080
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../tools/intel_reg_read 0x72080
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# Primary A control 0x70180
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# Primary B control 0x71180
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# Primary C control 0x72180
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../tools/intel_reg_read 0x70180
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../tools/intel_reg_read 0x71180
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../tools/intel_reg_read 0x72180
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# Sprite A control 0x70280
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# Sprite B control 0x71280
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# Sprite C control 0x72280
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../tools/intel_reg_read 0x70280
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../tools/intel_reg_read 0x71280
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../tools/intel_reg_read 0x72280
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# Sprite A size 0x70290
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# Sprite B size 0x71290
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# Sprite C size 0x72290
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../tools/intel_reg_read 0x70290
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../tools/intel_reg_read 0x71290
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../tools/intel_reg_read 0x72290
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# Sprite A scaling 0x70304
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# Sprite B scaling 0x71304
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# Sprite C scaling 0x72304
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../tools/intel_reg_read 0x70304
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../tools/intel_reg_read 0x71304
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../tools/intel_reg_read 0x72304
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# PCH DE Interrupt enable 0xC400C
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../tools/intel_reg_read 0xC400C
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# PCH DE Interrupt IIR 0xC4008
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../tools/intel_reg_read 0xC4008
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# PCH DE hotplug 0xC4030
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../tools/intel_reg_read 0xC4030
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# SERR_INT 0xC4040
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../tools/intel_reg_read 0xC4040
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# PCH DPLL A CTL 0xC6014
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# PCH DPLL A Divisor 0 0xC6040
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# PCH DPLL A Divisor 1 0xC6044
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../tools/intel_reg_read 0xC6014
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../tools/intel_reg_read 0xC6040
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../tools/intel_reg_read 0xC6044
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# PCH DPLL B CTL 0xC6018
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# PCH DPLL B Divisor 0 0xC6048
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# PCH DPLL B Divisor 1 0xC604C
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../tools/intel_reg_read 0xC6018
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../tools/intel_reg_read 0xC6048
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../tools/intel_reg_read 0xC604C
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# PCH DPLL DREF CTL 0xC6200
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../tools/intel_reg_read 0xC6200
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# PCH DPLL SEL 0xC7000
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../tools/intel_reg_read 0xC7000
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# PCH Panel Status 0xC7200
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../tools/intel_reg_read 0xC7200
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# PCH Panel Control 0xC7204
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../tools/intel_reg_read 0xC7204
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# Transcoder A timing 0xE0000-0xE004F
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# Transcoder B timing 0xE1000-0xE104F
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# Transcoder C timing 0xE2000-0xE204F
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../tools/intel_reg_read 0xE0000 -c 0x14;
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../tools/intel_reg_read 0xE1000 -c 0x14;
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../tools/intel_reg_read 0xE2000 -c 0x14;
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# Transcoder A DP CTL 0xE0300
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# Transcoder B DP CTL 0xE1300
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# Transcoder C DP CTL 0xE2300
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../tools/intel_reg_read 0xE0300
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../tools/intel_reg_read 0xE1300
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../tools/intel_reg_read 0xE2300
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# CRT DAC CTL 0xE1100
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../tools/intel_reg_read 0xE1100
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# HDMI/DVI B CTL 0xE1140
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# HDMI/DVI C CTL 0xE1150
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# HDMI/DVI D CTL 0xE1160
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../tools/intel_reg_read 0xE1140
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../tools/intel_reg_read 0xE1150
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../tools/intel_reg_read 0xE1160
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# LVDS 0xE1180
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../tools/intel_reg_read 0xE1180
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# DP B CTL 0xE4100
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# DP C CTL 0xE4200
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# DP D CTL 0xE4300
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../tools/intel_reg_read 0xE4100
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../tools/intel_reg_read 0xE4200
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../tools/intel_reg_read 0xE4300
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# Transcoder A config 0xF0008
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# FDI RX A CTL 0xF000C
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# FDI RX A MISC 0xF0010
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# FDI RX A IIR 0xF0014
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# FDI RX A IMR 0xF0018
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../tools/intel_reg_read 0xF0008 -c 5;
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# Transcoder B config 0xF1008
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# FDI RX B CTL 0xF100C
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# FDI RX B MISC 0xF1010
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# FDI RX B IIR 0xF1014
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# FDI RX B IMR 0xF1018
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../tools/intel_reg_read 0xF1008 -c 5;
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# Transcoder C config 0xF2008
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# FDI RX C CTL 0xF200C
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# FDI RX C MISC 0xF2010
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# FDI RX C IIR 0xF2014
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# FDI RX C IMR 0xF2018
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../tools/intel_reg_read 0xF2008 -c 5;
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#Check if frame and line counters are running
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../tools/intel_reg_read 0x44070
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../tools/intel_reg_read 0x70050
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../tools/intel_reg_read 0x71050
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../tools/intel_reg_read 0x72050
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sleep 2;
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../tools/intel_reg_read 0x44070
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../tools/intel_reg_read 0x70050
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../tools/intel_reg_read 0x71050
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../tools/intel_reg_read 0x72050
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