mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-08 16:36:14 +00:00
quick_dump: vlv: add missing display registers
Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This commit is contained in:
Imre Deak
parent
92378d3b77
commit
9da08fed03
@ -1,4 +1,6 @@
|
||||
vlv_display.txt
|
||||
vlv_pipe_a.txt
|
||||
vlv_pipe_b.txt
|
||||
vlv_display_base.txt
|
||||
vlv_dsi.txt
|
||||
base_interrupt.txt
|
||||
base_other.txt
|
||||
|
||||
@ -1,97 +0,0 @@
|
||||
('DPLLA_CTRL', '0x186014', '')
|
||||
('DPLLB_CTRL', '0x186018', '')
|
||||
('DPLLAMD_CRTL', '0x18601c', '')
|
||||
('DPLLBMD_CRTL', '0x186020', '')
|
||||
('RAWCLK_FREQ', '0x186024', '')
|
||||
('D_STAT', '0x186104', '')
|
||||
('DISPCLK_GATE_D', '0x186200', '')
|
||||
('DPPSR_CGDIS', '0x186204', '')
|
||||
('RAMCLK_GATE_D', '0x186210', '')
|
||||
('CPU_VGACNTRL', '0x001c1000', '')
|
||||
('HTOTAL_A', '0x001e0000', '')
|
||||
('HBLANK_A', '0x001e0004', '')
|
||||
('HSYNC_A', '0x001e0008', '')
|
||||
('VTOTAL_A', '0x001e000c', '')
|
||||
('VBLANK_A', '0x001e0010', '')
|
||||
('VSYNC_A', '0x001e0014', '')
|
||||
('PIPEASRC', '0x001e001c', '')
|
||||
('VSYNCSHIFT_A', '0x001e0028', '')
|
||||
('PIPEA_DATA_M1', '0x001e0030', '')
|
||||
('PIPEA_DATA_N1', '0x001e0034', '')
|
||||
('PIPEA_DATA_M2', '0x001e0038', '')
|
||||
('PIPEA_DATA_N2', '0x001e003c', '')
|
||||
('PIPEA_LINK_M1', '0x001e0040', '')
|
||||
('PIPEA_LINK_N1', '0x001e0044', '')
|
||||
('PIPEA_LINK_M2', '0x001e0048', '')
|
||||
('PIPEA_LINK_N2', '0x001e004c', '')
|
||||
('HTOTAL_B', '0x001e1000', '')
|
||||
('HBLANK_B', '0x001e1004', '')
|
||||
('HSYNC_B', '0x001e1008', '')
|
||||
('VTOTAL_B', '0x001e100c', '')
|
||||
('VBLANK_B', '0x001e1010', '')
|
||||
('VSYNC_B', '0x001e1014', '')
|
||||
('PIPEBSRC', '0x001e101c', '')
|
||||
('VSYNCSHIFT_B', '0x001e1028', '')
|
||||
('PIPEB_DATA_M1', '0x001e1030', '')
|
||||
('PIPEB_DATA_N1', '0x001e1034', '')
|
||||
('PIPEB_DATA_M2', '0x001e1038', '')
|
||||
('PIPEB_DATA_N2', '0x001e103c', '')
|
||||
('PIPEB_LINK_M1', '0x001e1040', '')
|
||||
('PIPEB_LINK_N1', '0x001e1044', '')
|
||||
('PIPEB_LINK_M2', '0x001e1048', '')
|
||||
('PIPEB_LINK_N2', '0x001e104c', '')
|
||||
('ADPA', '0x1e1100', '')
|
||||
('PORT_HOTPLUG_EN', '0x1e1110', '')
|
||||
('PORT_HOTPLUG_STAT', '0x1e1114', '')
|
||||
('SDVO_HDMIB', '0x1e1140', '')
|
||||
('SDVO_DP2', '0x1e1154', '')
|
||||
('HDMIC', '0x1e1160', '')
|
||||
('PORT_HOTPLUG_CTRL', '0x1e1164', '')
|
||||
('DP_B', '0x1e4100', '')
|
||||
('DP_C', '0x1e4200', '')
|
||||
('DPINVGTT', '0x001f002c', '')
|
||||
('DSPARB', '0x001f0030', '')
|
||||
('FW1', '0x001f0034', '')
|
||||
('FW2', '0x001f0038', '')
|
||||
('FW3', '0x001f003c', '')
|
||||
('FW4', '0x001f0070', '')
|
||||
('FW5', '0x001f0074', '')
|
||||
('FW6', '0x001f0078', '')
|
||||
('FW7', '0x001f007c', '')
|
||||
('DDL1', '0x001f0050', '')
|
||||
('DDL2', '0x001f0052', '')
|
||||
('DSPARB2', '0x001f0060', '')
|
||||
('DSPHOWM', '0x001f0064', '')
|
||||
('DSPHOWM1', '0x001f0068', '')
|
||||
('PIPEACONF', '0x001f0008', '')
|
||||
('PIPEASTAT', '0x001f0024', '')
|
||||
('DSPACNTR', '0x001f0180', '')
|
||||
('DSPABASE', '0x001f0184', '')
|
||||
('DSPASTRIDE', '0x001f0188', '')
|
||||
('DSPASURF', '0x001f019c', '')
|
||||
('DSPATILEOFF', '0x001f01a4', '')
|
||||
('PIPEBCONF', '0x001f1008', '')
|
||||
('PIPEBSTAT', '0x001f1024', '')
|
||||
('DSPBCNTR', '0x001f1180', '')
|
||||
('DSPBBASE', '0x001f1184', '')
|
||||
('DSPBSTRIDE', '0x001f1188', '')
|
||||
('DSPBSURF', '0x001f119c', '')
|
||||
('DSPBTILEOFF', '0x001f11a4', '')
|
||||
('PIPECCONF', '0x001f2008', '')
|
||||
('DSPCCNTR', '0x001f2180', '')
|
||||
('DSPCBASE', '0x001f2184', '')
|
||||
('DSPCSTRIDE', '0x001f2188', '')
|
||||
('DSPCSURF', '0x001f219c', '')
|
||||
('DSPCTILEOFF', '0x001f21a4', '')
|
||||
('PIPEA_PP_STATUS', '0x001e1200', '')
|
||||
('PIPEA_PP_CONTROL', '0x001e1204', '')
|
||||
('PIPEA_PP_ON_DELAYS', '0x001e1208', '')
|
||||
('PIPEA_PP_OFF_DELAYS', '0x001e120c', '')
|
||||
('PIPEA_PP_DIVISOR', '0x001e1210', '')
|
||||
('PIPEB_PP_STATUS', '0x001e1300', '')
|
||||
('PIPEB_PP_CONTROL', '0x001e1304', '')
|
||||
('PIPEB_PP_ON_DELAYS', '0x001e1308', '')
|
||||
('PIPEB_PP_OFF_DELAYS', '0x001e130c', '')
|
||||
('PIPEB_PP_DIVISOR', '0x001e1310', '')
|
||||
('BLC_PWM_CTL2', '0x1e1250', '')
|
||||
('BLC_PWM_CTL', '0x1e1254', '')
|
||||
180
tools/quick_dump/vlv_display_base.txt
Normal file
180
tools/quick_dump/vlv_display_base.txt
Normal file
@ -0,0 +1,180 @@
|
||||
('DPFLIPSTAT', '0x70028', '0x180000')
|
||||
('DPINVGTT', '0x7002C', '0x180000')
|
||||
|
||||
('DSPARB', '0x70030', '0x180000')
|
||||
('DSPARB2', '0x70060', '0x180000')
|
||||
|
||||
('DSPHOWM', '0x70064', '0x180000')
|
||||
('DSPHOWM1', '0x70068', '0x180000')
|
||||
('FW1', '0x70034', '0x180000')
|
||||
('FW2', '0x70038', '0x180000')
|
||||
('FW3', '0x7003C', '0x180000')
|
||||
('FW4', '0x70070', '0x180000')
|
||||
('FW5', '0x70074', '0x180000')
|
||||
('FW6', '0x70078', '0x180000')
|
||||
('FW7', '0x7007C', '0x180000')
|
||||
|
||||
('DDL1', '0x70050', '0x180000')
|
||||
('DDL2', '0x70054', '0x180000')
|
||||
|
||||
('VGACNTRL', '0x71400', '0x180000')
|
||||
|
||||
('CBR1', '0x70400', '0x180000')
|
||||
('CBR2', '0x70404', '0x180000')
|
||||
('CBR3', '0x7040C', '0x180000')
|
||||
('CBR4', '0x70450', '0x180000')
|
||||
('CCBR', '0x70408', '0x180000')
|
||||
|
||||
('SWF00', '0x70410', '0x180000')
|
||||
('SWF01', '0x70414', '0x180000')
|
||||
('SWF02', '0x70418', '0x180000')
|
||||
('SWF03', '0x7041C', '0x180000')
|
||||
('SWF04', '0x70420', '0x180000')
|
||||
('SWF05', '0x70424', '0x180000')
|
||||
('SWF06', '0x70428', '0x180000')
|
||||
('SWF07', '0x7042C', '0x180000')
|
||||
('SWF08', '0x70430', '0x180000')
|
||||
('SWF09', '0x70434', '0x180000')
|
||||
('SWF0A', '0x70438', '0x180000')
|
||||
('SWF0B', '0x7043C', '0x180000')
|
||||
('SWF0C', '0x70440', '0x180000')
|
||||
('SWF0D', '0x70444', '0x180000')
|
||||
('SWF0E', '0x70448', '0x180000')
|
||||
('SWF0F', '0x7044C', '0x180000')
|
||||
('SWF10', '0x71410', '0x180000')
|
||||
('SWF11', '0x71414', '0x180000')
|
||||
('SWF12', '0x71418', '0x180000')
|
||||
('SWF13', '0x7141C', '0x180000')
|
||||
('SWF14', '0x71420', '0x180000')
|
||||
('SWF15', '0x71424', '0x180000')
|
||||
('SWF16', '0x71428', '0x180000')
|
||||
('SWF17', '0x7142C', '0x180000')
|
||||
('SWF18', '0x71430', '0x180000')
|
||||
('SWF19', '0x71434', '0x180000')
|
||||
('SWF1A', '0x71438', '0x180000')
|
||||
('SWF1B', '0x7143C', '0x180000')
|
||||
('SWF1C', '0x71440', '0x180000')
|
||||
('SWF1D', '0x71444', '0x180000')
|
||||
('SWF1E', '0x71448', '0x180000')
|
||||
('SWF1F', '0x7144C', '0x180000')
|
||||
('SWF30', '0x72414', '0x180000')
|
||||
('SWF31', '0x72418', '0x180000')
|
||||
('SWF32', '0x7241C', '0x180000')
|
||||
|
||||
('PCSRC', '0x73000', '0x180000')
|
||||
('PCSTAT', '0x73004', '0x180000')
|
||||
('PCSRC2', '0x73008', '0x180000')
|
||||
('PCSTAT2', '0x7300C', '0x180000')
|
||||
|
||||
('PFIT_CONTROL', '0x61230', '0x180000')
|
||||
('PFIT_PGM_RATIOS', '0x61234', '0x180000')
|
||||
('PFIT_AUTO_RATION', '0x61238', '0x180000')
|
||||
('PFIT_INIT_PHASE', '0x6123C', '0x180000')
|
||||
|
||||
('GPIOCTL_0', '0x5010', '0x180000')
|
||||
('GPIOCTL_1', '0x5014', '0x180000')
|
||||
('GPIOCTL_2', '0x5018', '0x180000')
|
||||
('GPIOCTL_3', '0x501C', '0x180000')
|
||||
('GPIOCTL_4', '0x5020', '0x180000')
|
||||
|
||||
('GMBUS0', '0x5100', '0x180000')
|
||||
('GMBUS1', '0x5104', '0x180000')
|
||||
('GMBUS2', '0x5108', '0x180000')
|
||||
('GMBUS3', '0x510C', '0x180000')
|
||||
('GMBUS4', '0x5110', '0x180000')
|
||||
('GMBUS5', '0x5120', '0x180000')
|
||||
('GMBUS6', '0x5130', '0x180000')
|
||||
('GMBUS7', '0x5134', '0x180000')
|
||||
|
||||
('RAWCLK_FREQ', '0x6024', '0x180000')
|
||||
('GMBUSFREQ', '0x6510', '0x180000')
|
||||
('DSPCLK_GATE_D', '0x6200', '0x180000')
|
||||
('RAMCLK_GATE_D', '0x6210', '0x180000')
|
||||
('D_STATE', '0x6104', '0x180000')
|
||||
('DPPSR_CGDIS', '0x6204', '0x180000')
|
||||
('FW_BLC_SELF', '0x6500', '0x180000')
|
||||
('MI_ARB', '0x6504', '0x180000')
|
||||
('CZCLK_CDCLK_FREQ_RATIO', '0x6508', '0x180000')
|
||||
('GCI_CONTROL', '0x650C', '0x180000')
|
||||
|
||||
('ADPA', '0x61100', '0x180000')
|
||||
('CRTIO_DFX', '0x61104', '0x180000')
|
||||
|
||||
('PORT_HOTPLUG_EN', '0x61110', '0x180000')
|
||||
('PORT_HOTPLUG_STAT', '0x61114', '0x180000')
|
||||
|
||||
('HDMIB', '0x61140', '0x180000')
|
||||
('HDMIC', '0x61160', '0x180000')
|
||||
|
||||
('DP2', '0x61154', '0x180000')
|
||||
('DIGITAL_HPD_CTRL', '0x61164', '0x180000')
|
||||
('DV_DETERM', '0x61168', '0x180000')
|
||||
|
||||
('DP_AUX_CH_AKSV_HI', '0x64130', '0x180000')
|
||||
('DP_AUX_CH_AKSV_LO', '0x64134', '0x180000')
|
||||
|
||||
('DP_B', '0x64100', '0x180000')
|
||||
('DPB_AUX_CH_CTL', '0x64110', '0x180000')
|
||||
('DPB_AUX_CH_DATA1', '0x64114', '0x180000')
|
||||
('DPB_AUX_CH_DATA2', '0x64118', '0x180000')
|
||||
('DPB_AUX_CH_DATA3', '0x6411C', '0x180000')
|
||||
('DPB_AUX_CH_DATA4', '0x64120', '0x180000')
|
||||
('DPB_AUX_CH_DATA5', '0x64124', '0x180000')
|
||||
('DPB_AUX_TST', '0x64150', '0x180000')
|
||||
|
||||
('DP_C', '0x64200', '0x180000')
|
||||
('DPC_AUX_CH_CTL', '0x64210', '0x180000')
|
||||
('DPC_AUX_CH_DATA1', '0x64214', '0x180000')
|
||||
('DPC_AUX_CH_DATA2', '0x64218', '0x180000')
|
||||
('DPC_AUX_CH_DATA3', '0x6421C', '0x180000')
|
||||
('DPC_AUX_CH_DATA4', '0x64220', '0x180000')
|
||||
('DPC_AUX_CH_DATA5', '0x64224', '0x180000')
|
||||
('DPC_AUX_TST', '0x64228', '0x180000')
|
||||
|
||||
('DPIO_BONUS0', '0x64138', '0x180000')
|
||||
('DPIO_BONUS1', '0x6413C', '0x180000')
|
||||
('DPIO_BONUS2', '0x64140', '0x180000')
|
||||
('DPIO_BONUS0_READ_BACK', '0x64144', '0x180000')
|
||||
('DPIO_BONUS1_READ_BACK', '0x64148', '0x180000')
|
||||
('DPIO_BONUS2_READ_BACK', '0x6414C', '0x180000')
|
||||
|
||||
('DPA_PIX_GEN_CTRL', '0x61198', '0x180000')
|
||||
('DPA_PROG_PIXEL_DATA_1', '0x6119C', '0x180000')
|
||||
('DPA_PROG_PIXEL_DATA_2', '0x611A0', '0x180000')
|
||||
('DPA_PROG_PIXEL_DATA_3', '0x611A4', '0x180000')
|
||||
('DPA_PROG_PIXEL_DATA_4', '0x611A8', '0x180000')
|
||||
|
||||
('DPB_PIX_GEN_CTRL', '0x611B0', '0x180000')
|
||||
('DPB_PROG_PIXEL_DATA_1', '0x611B4', '0x180000')
|
||||
('DPB_PROG_PIXEL_DATA_2', '0x611B8', '0x180000')
|
||||
('DPB_PROG_PIXEL_DATA_3', '0x611BC', '0x180000')
|
||||
('DPB_PROG_PIXEL_DATA_4', '0x611C0', '0x180000')
|
||||
|
||||
('AUD_VID_DID', '0x62020', '0x180000')
|
||||
('AUD_RID', '0x62024', '0x180000')
|
||||
('AUD_PWRST', '0x6204C', '0x180000')
|
||||
('AUD_PORT_EN_HD_CFG', '0x6207C', '0x180000')
|
||||
('AUD_OUT_CH_STR', '0x62088', '0x180000')
|
||||
('AUD_PINW_CONNLNG_LIST', '0x620A8', '0x180000')
|
||||
('AUD_PINW_CONNLNG_SEL', '0x620AC', '0x180000')
|
||||
('AUD_CNTL_ST2', '0x620C0', '0x180000')
|
||||
('AUD_HDMIW_STATUS', '0x620D4', '0x180000')
|
||||
('AUD_SSID_DBG', '0x62F00', '0x180000')
|
||||
('AUD_PWST1_DBG', '0x62F04', '0x180000')
|
||||
('AUD_PWST2_DBG', '0x62F14', '0x180000')
|
||||
('AUD_PORT_EN_B_DBG', '0x62F20', '0x180000')
|
||||
('AUD_PWST3_DBG', '0x62F24', '0x180000')
|
||||
('AUD_PORT_EN_C_DBG', '0x62F28', '0x180000')
|
||||
('AUD_PORT_EN_D_DBG', '0x62F2C', '0x180000')
|
||||
('AUD_CHICKENBIT', '0x62F38', '0x180000')
|
||||
('AUD_CNTL_ST_B_DBG', '0x62F60', '0x180000')
|
||||
('AUD_HDMIW_INFOFR_B_DBG', '0x62F64', '0x180000')
|
||||
('AUD_CNTL_ST_C_DBG', '0x62F70', '0x180000')
|
||||
('AUD_HDMIW_INFOFR_C_DBG', '0x62F74', '0x180000')
|
||||
('AUD_CNTL_ST_D_DBG', '0x62F80', '0x180000')
|
||||
('AUD_HDMIW_INFOFR_D_DBG', '0x62F84', '0x180000')
|
||||
('AUD_CONFIG_DEFAULT2_REG_PORTB', '0x62F88', '0x180000')
|
||||
('AUD_CONFIG_DEFAULT2_REG_PORTC', '0x62F8C', '0x180000')
|
||||
('AUD_CONFIG_DEFAULT2_REG_PORTD', '0x62F90', '0x180000')
|
||||
('AUD_MCTSA', '0x62F94', '0x180000')
|
||||
('AUD_MCTSB', '0x62F98', '0x180000')
|
||||
Loading…
x
Reference in New Issue
Block a user