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https://github.com/tiagovignatti/intel-gpu-tools.git
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igt: Add gem_ctx_thrash to fill the GGTT with contexts
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
739790d7ed
commit
959a7db668
1
tests/.gitignore
vendored
1
tests/.gitignore
vendored
@ -29,6 +29,7 @@ gem_ctx_bad_exec
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gem_ctx_basic
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gem_ctx_create
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gem_ctx_exec
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gem_ctx_thrash
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gem_double_irq_loop
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gem_dummy_reloc_loop
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gem_evict_alignment
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@ -50,6 +50,8 @@ gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
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gem_close_race_LDADD = $(LDADD) -lpthread
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gem_ctx_basic_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
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gem_ctx_basic_LDADD = $(LDADD) -lpthread
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gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
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gem_ctx_thrash_LDADD = $(LDADD) -lpthread
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gem_fence_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
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gem_fence_thrash_LDADD = $(LDADD) -lpthread
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gem_fence_upload_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
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@ -100,6 +100,7 @@ TESTS_progs = \
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gem_ctx_bad_destroy \
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gem_ctx_basic \
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gem_ctx_create \
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gem_ctx_thrash \
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gem_double_irq_loop \
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gem_exec_big \
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gem_exec_blt \
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299
tests/gem_ctx_thrash.c
Normal file
299
tests/gem_ctx_thrash.c
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@ -0,0 +1,299 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <stdio.h>
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#include <string.h>
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#include <errno.h>
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#include <pthread.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#include "ioctl_wrappers.h"
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#include "igt_aux.h"
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#include "intel_chipset.h"
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#include "drmtest.h"
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IGT_TEST_DESCRIPTION("Fill the Gobal GTT with context objects and VMs\n");
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#define OBJECT_SIZE (1024 * 1024)
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#define NUM_THREADS 8
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static int fd;
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static unsigned devid;
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static igt_render_copyfunc_t render_copy;
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static dri_bo **all_bo;
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static int num_bo;
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static int bo_per_ctx;
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static drm_intel_context **all_ctx;
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static int num_ctx;
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static int ctx_per_thread;
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static void xchg_ptr(void *array, unsigned i, unsigned j)
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{
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void **A = array;
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swap(A[i], A[j]);
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}
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static void xchg_int(void *array, unsigned i, unsigned j)
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{
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int *A = array;
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swap(A[i], A[j]);
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}
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static int reopen(int _fd)
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{
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struct stat st;
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char name[128];
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igt_assert(fstat(_fd, &st) == 0);
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sprintf(name, "/dev/dri/card%u", (unsigned)(st.st_rdev & 0x7f));
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return open(name, O_RDWR);
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}
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static void *thread(void *bufmgr)
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{
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struct intel_batchbuffer *batch;
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dri_bo **bo;
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drm_intel_context **ctx;
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int c, b;
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batch = intel_batchbuffer_alloc(bufmgr, devid);
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bo = malloc(num_bo * sizeof(dri_bo *));
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igt_assert(bo);
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memcpy(bo, all_bo, num_bo * sizeof(dri_bo *));
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ctx = malloc(num_ctx * sizeof(drm_intel_context *));
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igt_assert(ctx);
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memcpy(ctx, all_ctx, num_ctx * sizeof(drm_intel_context *));
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igt_permute_array(ctx, num_ctx, xchg_ptr);
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for (c = 0; c < ctx_per_thread; c++) {
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igt_permute_array(bo, num_bo, xchg_ptr);
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for (b = 0; b < bo_per_ctx; b++) {
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struct igt_buf src, dst;
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src.bo = bo[b % num_bo];
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src.stride = 4;
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src.size = OBJECT_SIZE;
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src.tiling = I915_TILING_NONE;
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dst.bo = bo[(b+1) % num_bo];
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dst.stride = 4;
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dst.size = OBJECT_SIZE;
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dst.tiling = I915_TILING_NONE;
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render_copy(batch, ctx[c % num_ctx],
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&src, 0, 0, 1, 1, &dst, 0, 0);
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}
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}
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free(ctx);
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free(bo);
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intel_batchbuffer_free(batch);
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return NULL;
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}
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static int uses_ppgtt(int _fd)
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{
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struct drm_i915_getparam gp;
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int val = 0;
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memset(&gp, 0, sizeof(gp));
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gp.param = 18; /* HAS_ALIASING_PPGTT */
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gp.value = &val;
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if (drmIoctl(_fd, DRM_IOCTL_I915_GETPARAM, &gp))
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return 0;
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errno = 0;
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return val;
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}
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static void
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processes(void)
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{
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int *all_fds;
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uint64_t aperture;
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int ppgtt_mode;
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int ctx_size;
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int obj_size;
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int n;
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igt_skip_on_simulation();
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fd = drm_open_any_render();
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devid = intel_get_drm_devid(fd);
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aperture = gem_aperture_size(fd);
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ppgtt_mode = uses_ppgtt(fd);
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igt_require(ppgtt_mode);
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render_copy = igt_get_render_copyfunc(devid);
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igt_require_f(render_copy, "no render-copy function\n");
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if (ppgtt_mode > 1)
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ctx_size = aperture >> 10; /* Assume full-ppgtt of maximum size */
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else
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ctx_size = 64 << 10; /* Most gen require at least 64k for ctx */
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num_ctx = 3 * (aperture / ctx_size) / 2;
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igt_info("Creating %d contexts (assuming of size %d)\n",
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num_ctx, ctx_size);
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intel_require_memory(num_ctx, ctx_size, CHECK_RAM | CHECK_SWAP);
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all_fds = malloc(num_ctx * sizeof(int));
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igt_assert(all_fds);
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for (n = 0; n < num_ctx; n++) {
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all_fds[n] = reopen(fd);
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if (all_fds[n] == -1) {
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int err = errno;
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while (n--)
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close(all_fds[n]);
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free(all_fds);
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errno = err;
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igt_assert(0);
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}
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}
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num_bo = 2 * num_ctx;
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obj_size = (2 * aperture / num_bo + 4095) & -4096;
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igt_info("Creating %d surfaces (of size %d)\n", num_bo, obj_size);
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intel_require_memory(num_bo, obj_size, CHECK_RAM);
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igt_fork(child, NUM_THREADS) {
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drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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int c;
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igt_permute_array(all_fds, num_ctx, xchg_int);
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for (c = 0; c < num_ctx; c++) {
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struct igt_buf src, dst;
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bufmgr = drm_intel_bufmgr_gem_init(all_fds[c], 4096);
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igt_assert(bufmgr);
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batch = intel_batchbuffer_alloc(bufmgr, devid);
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src.bo = drm_intel_bo_alloc(bufmgr, "", obj_size, 0);
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igt_assert(src.bo);
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src.stride = 4;
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src.size = obj_size;
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src.tiling = I915_TILING_NONE;
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dst.bo = drm_intel_bo_alloc(bufmgr, "", obj_size, 0);
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igt_assert(dst.bo);
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dst.stride = 4;
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dst.size = obj_size;
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dst.tiling = I915_TILING_NONE;
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render_copy(batch, NULL,
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&src, 0, 0, 1, 1, &dst, 0, 0);
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intel_batchbuffer_free(batch);
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drm_intel_bo_unreference(src.bo);
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drm_intel_bo_unreference(dst.bo);
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drm_intel_bufmgr_destroy(bufmgr);
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}
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}
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for (n = 0; n < num_ctx; n++)
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close(all_fds[n]);
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free(all_fds);
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close(fd);
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}
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static void
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threads(void)
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{
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pthread_t threads[NUM_THREADS];
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drm_intel_bufmgr *bufmgr;
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uint64_t aperture;
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int ppgtt_mode;
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int ctx_size;
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int n;
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igt_skip_on_simulation();
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fd = drm_open_any_render();
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devid = intel_get_drm_devid(fd);
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aperture = gem_aperture_size(fd);
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ppgtt_mode = uses_ppgtt(fd);
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igt_require(ppgtt_mode);
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render_copy = igt_get_render_copyfunc(devid);
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igt_require_f(render_copy, "no render-copy function\n");
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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igt_assert(bufmgr);
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if (ppgtt_mode > 1)
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ctx_size = aperture >> 10; /* Assume full-ppgtt of maximum size */
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else
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ctx_size = 64 << 10; /* Most gen require at least 64k for ctx */
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num_ctx = 3 * (aperture / ctx_size) / 2;
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igt_info("Creating %d contexts (assuming of size %d)\n",
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num_ctx, ctx_size);
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intel_require_memory(num_ctx, ctx_size, CHECK_RAM | CHECK_SWAP);
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all_ctx = malloc(num_ctx * sizeof(drm_intel_context *));
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igt_assert(all_ctx);
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for (n = 0; n < num_ctx; n++) {
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all_ctx[n] = drm_intel_gem_context_create(bufmgr);
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igt_assert(all_ctx[n]);
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}
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num_bo = 3 * (aperture / OBJECT_SIZE) / 2;
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igt_info("Creating %d surfaces (of size %d)\n", num_bo, OBJECT_SIZE);
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intel_require_memory(num_bo, OBJECT_SIZE, CHECK_RAM);
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all_bo = malloc(num_bo * sizeof(dri_bo *));
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igt_assert(all_bo);
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for (n = 0; n < num_bo; n++) {
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all_bo[n] = drm_intel_bo_alloc(bufmgr, "", OBJECT_SIZE, 0);
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igt_assert(all_bo[n]);
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}
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ctx_per_thread = 5 * num_ctx / NUM_THREADS / 4;
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bo_per_ctx = 2 * num_bo / ctx_per_thread;
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for (n = 0; n < NUM_THREADS; n++)
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pthread_create(&threads[n], NULL, thread, bufmgr);
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for (n = 0; n < NUM_THREADS; n++)
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pthread_join(threads[n], NULL);
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drm_intel_bufmgr_destroy(bufmgr);
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close(fd);
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}
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igt_main
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{
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igt_subtest("processes")
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processes();
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igt_subtest("threads")
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threads();
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}
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