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https://github.com/tiagovignatti/intel-gpu-tools.git
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rendercopy/bdw: Fix the original implementation
For posterity, I've squashed these commits against Damien's request. rendercopy/gen8: Fix the include guards rendercopy/gen8: Update the 3DSTATE_MULTISAMPLE opcode The opcode has changed in BDW. rendercopy/gen8: Add the VF_TOPOLOGY state The primitive type has moved out of the 3DPRIMITIVE to its own state, VF_TOPOLOGY. rendercopy/gen8: Fixup 3STATE_PS Update the state to the latest BSpec, in particular the thread count was using a wrong shift and we were missing kernel2 offset. rendercopy/gen8: Update 3DSTATE_BASE_ADDRESS This state has seen its fields moved around a bit, follow the BSpec. rendercopy/gen8: Allocate 64 VUEs The simulator screams at us if we try to allocate less than that. rendercopy/gen8: Surface states have to be 64 bytes a aligned rendercopy/gen8: Vertical/horizontal align 2 does not exist any more So set them to 4. This should not matter with rendercopy (which is not using compressed textures), but it makes the simulator moan. rendercopy/gen8: Make sure the vertex buffer is 8 bytes aligned rendercopy/gen8: Adjust 3DSTATE_VERTEX_BUFFERS for gen8 The address of the buffer is now on 48 bits. Also the size was computed as offset + size where the field is really the size of the buffer itself, not the end address. rendercopy/gen8: Update the SF/SBE states for gen8 gen8 has a few changes around those states and a new ones RASTER and SBE_SWIZ. rendercopy/gen8: Add the PS_EXTRA and PS_BLEND states rendercopy/gen8: Fix building with DEBUG_RENDERCOPY defined The forward declaration was missing the final ';'. Let's move the whole function at the top instead. rendercopy/gen8: Update the PS and CONSTANT_PS states rendercopy/gen8: Fix the red channel selection Make it output red. rendercopy/gen8: Update the write -1 shader With the latest assembler changes from Haihao. rendercopy/gen8: Remove blit.g8a There is no diff between this file and blig.g7a. Remove it. rendercopy/gen8: Fix the surface relocation offset The surface base address is now at dwords 8/9 so the relocation has to mirror the change. rendercopy/gen8: Add the VF_INSTANCING state Should work without, but doesn't hurt to add it. rendercopy/gen8: Set the Attribule enable field in PS_EXTRA When the SF is set up to output some attributes, the pixel shader also have to be told there's attributes to care about. rendercopy/gen8: Set the force bits to read URB offset/length If we want to override the URB offset/length in the SBE state itself, we need to set the force bits on (new in gen8) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Damien Lespiau
Ben Widawsky
parent
3f0714a860
commit
91e5897246
@ -1,5 +1,5 @@
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#ifndef GEN7_RENDER_H
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#define GEN7_RENDER_H
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#ifndef GEN8_RENDER_H
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#define GEN8_RENDER_H
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#include "gen6_render.h"
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@ -13,7 +13,16 @@
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#define GEN7_3DSTATE_DEPTH_BUFFER GEN6_3D(3, 0, 0x05)
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#define GEN7_3DSTATE_STENCIL_BUFFER GEN6_3D(3, 0, 0x06)
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#define GEN7_3DSTATE_HIER_DEPTH_BUFFER GEN6_3D(3, 0, 0x07)
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#define GEN8_3DSTATE_MULTISAMPLE GEN6_3D(3, 0, 0x0d)
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# define GEN8_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4)
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# define GEN8_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4)
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# define GEN8_3DSTATE_MULTISAMPLE_NUMSAMPLES_1 (0 << 1)
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# define GEN8_3DSTATE_MULTISAMPLE_NUMSAMPLES_2 (1 << 1)
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# define GEN8_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1)
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# define GEN8_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1)
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# define GEN9_3DSTATE_MULTISAMPLE_NUMSAMPLES_16 (4 << 1)
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#define GEN8_3DSTATE_VF_INSTANCING GEN6_3D(3, 0, 0x49)
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#define GEN7_3DSTATE_GS GEN6_3D(3, 0, 0x11)
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#define GEN7_3DSTATE_CONSTANT_GS GEN6_3D(3, 0, 0x16)
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#define GEN7_3DSTATE_CONSTANT_HS GEN6_3D(3, 0, 0x19)
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@ -23,9 +32,24 @@
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#define GEN7_3DSTATE_DS GEN6_3D(3, 0, 0x1d)
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#define GEN7_3DSTATE_STREAMOUT GEN6_3D(3, 0, 0x1e)
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#define GEN7_3DSTATE_SBE GEN6_3D(3, 0, 0x1f)
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# define GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH (1 << 29)
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# define GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET (1 << 28)
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# define GEN7_SBE_NUM_OUTPUTS_SHIFT 22
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# define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11
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# define GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT 5
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#define GEN8_3DSTATE_SBE_SWIZ GEN6_3D(3, 0, 0x51)
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#define GEN8_3DSTATE_RASTER GEN6_3D(3, 0, 0x50)
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# define GEN8_RASTER_FRONT_WINDING_CCW (1 << 21)
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# define GEN8_RASTER_CULL_NONE (1 << 16)
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#define GEN7_3DSTATE_PS GEN6_3D(3, 0, 0x20)
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#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP \
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GEN6_3D(3, 0, 0x21)
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#define GEN8_3DSTATE_PS_BLEND GEN6_3D(3, 0, 0x4d)
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# define GEN8_PS_BLEND_HAS_WRITEABLE_RT (1 << 30)
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#define GEN8_3DSTATE_PS_EXTRA GEN6_3D(3,0, 0x4f)
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# define GEN8_PSX_PIXEL_SHADER_VALID (1 << 31)
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# define GEN8_PSX_ATTRIBUTE_ENABLE (1 << 8)
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#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC GEN6_3D(3, 0, 0x23)
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#define GEN7_3DSTATE_BLEND_STATE_POINTERS GEN6_3D(3, 0, 0x24)
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#define GEN7_3DSTATE_DS_STATE_POINTERS GEN6_3D(3, 0, 0x25)
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@ -41,6 +65,8 @@
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#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS GEN6_3D(3, 0, 0x2e)
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#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS GEN6_3D(3, 0, 0x2f)
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#define GEN8_3DSTATE_VF_TOPOLOGY GEN6_3D(3, 0, 0x4b)
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#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS GEN6_3D(3, 1, 0x12)
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#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS GEN6_3D(3, 1, 0x13)
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#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS GEN6_3D(3, 1, 0x14)
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@ -49,13 +75,11 @@
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/* Some random bits that we care about */
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#define GEN7_VB0_BUFFER_ADDR_MOD_EN (1 << 14)
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#define GEN7_WM_DISPATCH_ENABLE (1 << 29)
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#define GEN7_3DSTATE_PS_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 11)
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#define GEN7_3DSTATE_PS_ATTRIBUTE_ENABLED (1 << 10)
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/* Random shifts */
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#define GEN7_3DSTATE_WM_MAX_THREADS_SHIFT 24
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#define HSW_3DSTATE_WM_MAX_THREADS_SHIFT 23
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#define GEN8_3DSTATE_PS_MAX_THREADS_SHIFT 23
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/* Shamelessly ripped from mesa */
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struct gen8_surface_state
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@ -7,7 +7,13 @@
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#define VERTEX_SIZE (3*4)
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#if DEBUG_RENDERCPY
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static void dump_batch(struct intel_batchbuffer *batch)
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static void dump_batch(struct intel_batchbuffer *batch) {
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int fd = open("/tmp/i965-batchbuffers.dump", O_WRONLY | O_CREAT, 0666);
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if (fd != -1) {
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write(fd, batch->buffer, 4096);
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fd = close(fd);
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}
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}
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#else
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#define dump_batch(x) do { } while(0)
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#endif
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@ -33,15 +39,15 @@ static const uint32_t ps_kernel[][4] = {
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{ 0x05800031, 0x200022e0, 0x0e000e00, 0x90031000 },
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#else
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/* Write all -1 */
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{ 0x00600001, 0x2e000061, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2e200061, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2e400061, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2e600061, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2e800061, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2ea00061, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2ec00061, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2ee00061, 0x00000000, 0x3f800000 },
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{ 0x05800031, 0x20001e3c, 0x00000e00, 0x90031000 },
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{ 0x00600001, 0x2e000608, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2e200608, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2e400608, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2e600608, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2e800608, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2ea00608, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2ec00608, 0x00000000, 0x3f800000 },
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{ 0x00600001, 0x2ee00608, 0x00000000, 0x3f800000 },
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{ 0x05800031, 0x200022e0, 0x0e000e00, 0x90031000 },
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#endif
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};
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@ -107,10 +113,12 @@ gen8_bind_buf(struct intel_batchbuffer *batch, struct scratch_buf *buf,
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read_domain = I915_GEM_DOMAIN_SAMPLER;
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}
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ss = batch_alloc(batch, sizeof(*ss), 32);
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ss = batch_alloc(batch, sizeof(*ss), 64);
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ss->ss0.surface_type = GEN6_SURFACE_2D;
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ss->ss0.surface_format = format;
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ss->ss0.render_cache_read_write = 1;
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ss->ss0.vertical_alignment = 1; /* align 4 */
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ss->ss0.horizontal_alignment = 1; /* align 4 */
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if (buf->tiling == I915_TILING_X)
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ss->ss0.tiled_mode = 2;
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else if (buf->tiling == I915_TILING_Y)
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@ -119,7 +127,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, struct scratch_buf *buf,
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ss->ss8.base_addr = buf->bo->offset;
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ret = drm_intel_bo_emit_reloc(batch->bo,
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batch_offset(batch, ss) + 4,
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batch_offset(batch, ss) + 8 * 4,
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buf->bo, 0,
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read_domain, write_domain);
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assert(ret == 0);
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@ -128,7 +136,7 @@ gen8_bind_buf(struct intel_batchbuffer *batch, struct scratch_buf *buf,
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ss->ss2.width = buf_width(buf) - 1;
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ss->ss3.pitch = buf->stride - 1;
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ss->ss7.shader_chanel_select_a = 4;
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ss->ss7.shader_chanel_select_r = 4;
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ss->ss7.shader_chanel_select_g = 5;
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ss->ss7.shader_chanel_select_b = 6;
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ss->ss7.shader_chanel_select_a = 7;
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@ -190,6 +198,7 @@ gen7_fill_vertex_buffer_data(struct intel_batchbuffer *batch,
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uint32_t width, uint32_t height) {
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void *ret;
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batch_align(batch, 8);
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ret = batch->ptr;
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emit_vertex_2s(batch, dst_x + width, dst_y + height);
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@ -272,14 +281,13 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
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*/
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static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch,
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uint32_t offset) {
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OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (4 * 1 - 1));
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OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2));
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OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */
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VB0_VERTEXDATA |
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GEN7_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */
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VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset);
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset + (VERTEX_SIZE * 3) - 1);
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OUT_BATCH(0);
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OUT_BATCH(3 * VERTEX_SIZE);
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}
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static uint32_t
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@ -361,30 +369,47 @@ gen7_emit_push_constants(struct intel_batchbuffer *batch) {
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}
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static void
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gen7_emit_state_base_address(struct intel_batchbuffer *batch) {
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OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
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/* general (stateless) */
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/* surface */
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/* instruction */
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/* indirect */
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/* dynamic */
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gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
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OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (16 - 2));
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/* general */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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/* stateless data port */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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/* surface */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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/* dynamic */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
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0, BASE_ADDRESS_MODIFY);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(0xfffff000 | BASE_ADDRESS_MODIFY); // copied from mesa
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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/* indirect */
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* instruction */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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/* general state buffer size */
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OUT_BATCH(0xfffff000 | 1);
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/* dynamic state buffer size */
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OUT_BATCH(1 << 12 | 1);
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/* indirect object buffer size */
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OUT_BATCH(0xfffff000 | 1);
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/* intruction buffer size */
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OUT_BATCH(1 << 12);
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}
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static void
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gen7_emit_urb(struct intel_batchbuffer *batch) {
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/* XXX: Min valid values from mesa */
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const int vs_entries = 32;
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const int vs_entries = 64;
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const int vs_size = 2;
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const int vs_start = 2;
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@ -408,8 +433,8 @@ gen8_emit_cc(struct intel_batchbuffer *batch) {
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}
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static void
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gen7_emit_multisample(struct intel_batchbuffer *batch) {
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OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | 2);
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gen8_emit_multisample(struct intel_batchbuffer *batch) {
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OUT_BATCH(GEN8_3DSTATE_MULTISAMPLE | 2);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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@ -537,49 +562,52 @@ gen7_emit_clip(struct intel_batchbuffer *batch) {
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}
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static void
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gen7_emit_sf(struct intel_batchbuffer *batch) {
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OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
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#ifdef GPU_HANG
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OUT_BATCH(0 << 22 | 1 << 11 | 1 << 4);
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#else
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OUT_BATCH(1 << 22 | 1 << 11 | 1 << 4);
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#endif
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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gen8_emit_sf(struct intel_batchbuffer *batch)
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{
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int i;
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OUT_BATCH(GEN7_3DSTATE_SBE | (4 - 2));
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OUT_BATCH(1 << GEN7_SBE_NUM_OUTPUTS_SHIFT |
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GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH |
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GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET |
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1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
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1 << GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN8_3DSTATE_SBE_SWIZ | (11 - 2));
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for (i = 0; i < 8; i++)
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
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OUT_BATCH(GEN8_3DSTATE_RASTER | (5 - 2));
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OUT_BATCH(GEN8_RASTER_FRONT_WINDING_CCW | GEN8_RASTER_CULL_NONE);
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
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// OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_SF | (4 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen8_emit_ps(struct intel_batchbuffer *batch, uint32_t kernel) {
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const int max_threads = 86;
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const int max_threads = 63;
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OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2));
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OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
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/* XXX: I don't understand the BARYCENTRIC stuff, but it
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OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2));
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OUT_BATCH(/* XXX: I don't understand the BARYCENTRIC stuff, but it
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* appears we need it to put our setup data in the place we
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* expect (g6, see below) */
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GEN7_3DSTATE_PS_PERSPECTIVE_PIXEL_BARYCENTRIC);
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (7-2));
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OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (11-2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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@ -587,19 +615,26 @@ gen8_emit_ps(struct intel_batchbuffer *batch, uint32_t kernel) {
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN7_3DSTATE_PS | (10-2));
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OUT_BATCH(GEN7_3DSTATE_PS | (12-2));
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OUT_BATCH(kernel);
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OUT_BATCH(0); /* kernel hi */
|
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OUT_BATCH(1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF |
|
||||
2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
|
||||
OUT_BATCH(0); /* scratch space stuff */
|
||||
OUT_BATCH(0); /* scratch hi */
|
||||
OUT_BATCH((max_threads - 1) << GEN7_3DSTATE_WM_MAX_THREADS_SHIFT |
|
||||
GEN7_3DSTATE_PS_ATTRIBUTE_ENABLED |
|
||||
OUT_BATCH((max_threads - 1) << GEN8_3DSTATE_PS_MAX_THREADS_SHIFT |
|
||||
GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
|
||||
OUT_BATCH(6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT);
|
||||
OUT_BATCH(0); // kernel 1
|
||||
OUT_BATCH(0); /* kernel 1 hi */
|
||||
OUT_BATCH(0); // kernel 2
|
||||
OUT_BATCH(0); /* kernel 2 hi */
|
||||
|
||||
OUT_BATCH(GEN8_3DSTATE_PS_BLEND | (2 - 2));
|
||||
OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT);
|
||||
|
||||
OUT_BATCH(GEN8_3DSTATE_PS_EXTRA | (2 - 2));
|
||||
OUT_BATCH(GEN8_PSX_PIXEL_SHADER_VALID | GEN8_PSX_ATTRIBUTE_ENABLE);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -637,11 +672,21 @@ gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct scratch_buf
|
||||
OUT_BATCH(0);
|
||||
}
|
||||
|
||||
/* Vertex elements MUST be defined before this according to spec */
|
||||
static void gen7_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset)
|
||||
static void gen8_emit_vf_topology(struct intel_batchbuffer *batch)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
|
||||
OUT_BATCH(GEN8_3DSTATE_VF_TOPOLOGY);
|
||||
OUT_BATCH(_3DPRIM_RECTLIST);
|
||||
}
|
||||
|
||||
/* Vertex elements MUST be defined before this according to spec */
|
||||
static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset)
|
||||
{
|
||||
OUT_BATCH(GEN8_3DSTATE_VF_INSTANCING | (3 - 2));
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
|
||||
OUT_BATCH(0); /* gen8+ ignore the topology type field */
|
||||
OUT_BATCH(3); /* vertex count */
|
||||
OUT_BATCH(0); /* We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */
|
||||
OUT_BATCH(1); /* single instance */
|
||||
@ -719,7 +764,7 @@ void gen8_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
|
||||
gen7_emit_push_constants(batch);
|
||||
|
||||
gen7_emit_state_base_address(batch);
|
||||
gen8_emit_state_base_address(batch);
|
||||
|
||||
OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC);
|
||||
OUT_BATCH(viewport.cc_state);
|
||||
@ -730,7 +775,7 @@ void gen8_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
|
||||
gen8_emit_cc(batch);
|
||||
|
||||
gen7_emit_multisample(batch);
|
||||
gen8_emit_multisample(batch);
|
||||
|
||||
gen7_emit_null_state(batch);
|
||||
|
||||
@ -740,7 +785,7 @@ void gen8_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
|
||||
gen7_emit_clip(batch);
|
||||
|
||||
gen7_emit_sf(batch);
|
||||
gen8_emit_sf(batch);
|
||||
|
||||
OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS);
|
||||
OUT_BATCH(ps_binding_table);
|
||||
@ -762,7 +807,8 @@ void gen8_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
gen7_emit_vertex_buffer(batch, vertex_buffer);
|
||||
gen6_emit_vertex_elements(batch);
|
||||
|
||||
gen7_emit_primitive(batch, vertex_buffer);
|
||||
gen8_emit_vf_topology(batch);
|
||||
gen8_emit_primitive(batch, vertex_buffer);
|
||||
|
||||
OUT_BATCH(MI_BATCH_BUFFER_END);
|
||||
|
||||
@ -774,13 +820,3 @@ void gen8_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
gen6_render_flush(batch, batch_end);
|
||||
intel_batchbuffer_reset(batch);
|
||||
}
|
||||
|
||||
#if DEBUG_RENDERCPY
|
||||
static void dump_batch(struct intel_batchbuffer *batch) {
|
||||
int fd = open("/tmp/i965-batchbuffers.dump", O_WRONLY | O_CREAT, 0666);
|
||||
if (fd != -1) {
|
||||
write(fd, batch->buffer, 4096);
|
||||
fd = close(fd);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,66 +0,0 @@
|
||||
/* Assemble with ".../intel-gen4asm/src/intel-gen4asm -g 7" */
|
||||
|
||||
|
||||
/* Move pixels into g10-g13. The pixel shaader does not load what you want. It
|
||||
* loads the input data for a plane function to calculate what you want. The
|
||||
* following is boiler plate code to move our normalized texture coordinates
|
||||
* (u,v) into g10-g13. It does this 4 subspans (16 pixels) at a time.
|
||||
*
|
||||
* This should do the same thing, but it doesn't work for some reason.
|
||||
* pln(16) g10 g6<0,1,0>F g2<8,8,1>F { align1 };
|
||||
* pln(16) g12 g6.16<1>F g2<8,8,1>F { align1 };
|
||||
*/
|
||||
/* U */
|
||||
pln (8) g10<1>F g6.0<0,1,0>F g2.0<8,8,1>F { align1 }; /* pixel 0-7 */
|
||||
pln (8) g11<1>F g6.0<0,1,0>F g4.0<8,8,1>F { align1 }; /* pixel 8-15 */
|
||||
/* V */
|
||||
pln (8) g12<1>F g6.16<0,1,0> g2.0<8,8,1>F { align1 }; /* pixel 0-7 */
|
||||
pln (8) g13<1>F g6.16<0,1,0> g4.0<8,8,1>F { align1 }; /* pixel 8-15 */
|
||||
|
||||
|
||||
/* Next the we want the sampler to fetch the src texture (ie. src buffer). This
|
||||
* is done with a pretty simple send message. The output goes to g112, which is
|
||||
* exactly what we're supposed to use in our final send message.
|
||||
* In intel-gen4asm, we should end up parsed by the following rule:
|
||||
* predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions
|
||||
*
|
||||
* Send message descriptor:
|
||||
* 28:25 = message len = 4 // our 4 registers have 16 pixels
|
||||
* 24:20 = response len = 8 // Each pixel is RGBA32, so we need 8 registers
|
||||
* 19:19 = header present = 0
|
||||
* 18:17 = SIMD16 = 2
|
||||
* 16:12 = TYPE = 0 (regular sample)
|
||||
* 11:08 = Sampler index = ignored/0
|
||||
* 7:0 = binding table index = src = 1
|
||||
* 0x8840001
|
||||
*
|
||||
* Send message extra descriptor
|
||||
* 5:5 = End of Thread = 0
|
||||
* 3:0 = Target Function ID = SFID_SAMPLER (2)
|
||||
* 0x2
|
||||
*/
|
||||
|
||||
send(16) g112 g10 0x2 0x8840001 { align1 };
|
||||
|
||||
/* g112-g119 now contains the sample source input, and all we must do is write
|
||||
* it out to the destination render target. This is done with the send message
|
||||
* as well. The only extra bits are to terminate the pixel shader.
|
||||
*
|
||||
* Send message descriptor:
|
||||
* 28:25 = message len = 8 // 16 pixels RGBA32
|
||||
* 24:20 = response len = 0
|
||||
* 19:19 = header present = 0
|
||||
* 17:14 = message type = Render Target Write (12)
|
||||
* 12:12 = Last Render Target Select = 1
|
||||
* 10:08 = Message Type = SIMD16 (0)
|
||||
* 07:00 = Binding Table Index = dest = 0
|
||||
* 0x10031000
|
||||
*
|
||||
* Send message extra descriptor
|
||||
* 5:5 = End of Thread = 1
|
||||
* 3:0 = Target Function ID = SFID_DP_RC (5)
|
||||
* 0x25
|
||||
*/
|
||||
send(16) null g112 0x25 0x10031000 { align1, EOT };
|
||||
|
||||
/* vim: set ft=c ts=4 sw=2 tw=80 et: */
|
||||
Loading…
x
Reference in New Issue
Block a user