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assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8

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Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
  >add.sat (16) r[a0.5,0]<1>:uw     r[a0.5,0]<16;16,1>:uw  0x0080:uw
  >add.sat (16) r[a0.5,32]<1>:uw    r[a0.5,32]<16;16,1>:uw 0x0080:uw

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Zhao Yakui
2013-04-09 09:59:15 +08:00
committed by Ben Widawsky
parent 60c9b41e11
commit 88e5f1fdf8
3 changed files with 101 additions and 15 deletions
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assembler/gram.y
+12
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@@ -294,6 +294,12 @@ static bool validate_dst_reg(struct brw_program_instruction *insn, struct brw_re
return false;
}
if (reg->address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER &&
access_mode(insn) == BRW_ALIGN_16) {
fprintf(stderr, "error: indirect Dst addr mode in align16 instruction\n");
return false;
}
return true;
}
@@ -317,6 +323,12 @@ static bool validate_src_reg(struct brw_program_instruction *insn,
return false;
}
if (reg.address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER &&
access_mode(insn) == BRW_ALIGN_16) {
fprintf(stderr, "error: indirect Source addr mode in align16 instruction\n");
return false;
}
assert(reg.hstride >= 0 && reg.hstride < ARRAY_SIZE(hstride_for_reg));
hstride = hstride_for_reg[reg.hstride];