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assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8

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Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
  >add.sat (16) r[a0.5,0]<1>:uw     r[a0.5,0]<16;16,1>:uw  0x0080:uw
  >add.sat (16) r[a0.5,32]<1>:uw    r[a0.5,32]<16;16,1>:uw 0x0080:uw

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Zhao Yakui
2013-04-09 09:59:15 +08:00
committed by Ben Widawsky
parent 60c9b41e11
commit 88e5f1fdf8
3 changed files with 101 additions and 15 deletions
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assembler/gen8_instruction.h
+24
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@@ -224,8 +224,32 @@ F(cre_message_type, 110, 109)
F(cre_binding_table_index, 103, 96)
/** @} */
/* Addr Mode */
F(dst_addr_mode, 63, 63)
F(src0_addr_mode, 79, 79)
F(src1_addr_mode, 111, 111)
/* Indirect access mode for Align1. */
F(dst_ida1_sub_nr, 60, 57)
F(src0_ida1_sub_nr, 76, 73)
F(src1_ida1_sub_nr, 108, 105)
/* Imm[8:0] of Immediate addr offset under Indirect mode */
F(dst_ida1_imm8, 56, 48)
F(src0_ida1_imm8, 72, 64)
F(src1_ida1_imm8, 104, 96)
/* Imm Bit9 of Immediate addr offset under Indirect mode */
F(dst_ida1_imm9, 47, 47)
F(src0_ida1_imm9, 95, 95)
F(src1_ida1_imm9, 121, 121)
#undef F
#define IMM8_MASK 0x1FF
#define IMM9_MASK 0x200
/**
* Flow control instruction bits:
* @{