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https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-20 06:16:13 +00:00
mmio: use intel_iosf.c for DPIO reads and writes
This makes it a bit more like the kernel, so we can go poke at DPIO and other IOSF regs a bit more easily. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Jesse Barnes
parent
d1b5823ee7
commit
81095305f4
@ -35,7 +35,6 @@ libintel_tools_la_SOURCES = \
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rendercopy_gen8.c \
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rendercopy.h \
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intel_reg_map.c \
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intel_dpio.c \
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intel_iosf.c \
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igt_kms.c \
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igt_kms.h \
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105
lib/intel_dpio.c
105
lib/intel_dpio.c
@ -1,105 +0,0 @@
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/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Vijay Purushothaman <vijay.a.purushothaman@intel.com>
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*
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*/
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <err.h>
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#include "intel_gpu_tools.h"
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static uint32_t intel_display_reg_read(uint32_t reg)
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{
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struct pci_device *dev = intel_get_pci_device();
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if (IS_VALLEYVIEW(dev->device_id))
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reg += VLV_DISPLAY_BASE;
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return (*(volatile uint32_t*)((volatile char*)mmio + reg));
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}
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static void intel_display_reg_write(uint32_t reg, uint32_t val)
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{
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volatile uint32_t *ptr;
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struct pci_device *dev = intel_get_pci_device();
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if (IS_VALLEYVIEW(dev->device_id))
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reg += VLV_DISPLAY_BASE;
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ptr = (volatile uint32_t*)((volatile char*)mmio + reg);
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*ptr = val;
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}
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static int get_dpio_port(int phy) {
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struct pci_device *dev = intel_get_pci_device();
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int dpio_port;
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if (IS_VALLEYVIEW(dev->device_id))
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dpio_port = DPIO_PORTID;
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return dpio_port;
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}
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/*
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* In SoCs like Valleyview some of the PLL & Lane control registers
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* can be accessed only through IO side band fabric called DPIO
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*/
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uint32_t
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intel_dpio_reg_read(uint32_t reg, int phy)
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{
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/* Check whether the side band fabric is ready to accept commands */
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do {
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usleep(1);
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} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
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intel_display_reg_write(DPIO_REG, reg);
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intel_display_reg_write(DPIO_PKT, DPIO_RID |
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DPIO_OP_READ | get_dpio_port(phy) | DPIO_BYTE);
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do {
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usleep(1);
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} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
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return intel_display_reg_read(DPIO_DATA);
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}
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/*
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* In SoCs like Valleyview some of the PLL & Lane control registers
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* can be accessed only through IO side band fabric called DPIO
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*/
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void
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intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
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{
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/* Check whether the side band fabric is ready to accept commands */
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do {
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usleep(1);
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} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
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intel_display_reg_write(DPIO_DATA, val);
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intel_display_reg_write(DPIO_REG, reg);
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intel_display_reg_write(DPIO_PKT, DPIO_RID |
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DPIO_OP_WRITE | get_dpio_port(phy) | DPIO_BYTE);
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do {
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usleep(1);
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} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
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}
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@ -7,12 +7,14 @@
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#define TIMEOUT_US 500000
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static int vlv_punit_rw(uint32_t port, uint8_t opcode, uint8_t addr,
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uint32_t *val)
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static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint8_t addr,
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uint32_t *val)
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{
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volatile uint32_t *ptr;
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int timeout = 0;
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uint32_t cmd, devfn, be, bar;
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int is_read = (opcode == PUNIT_OPCODE_REG_READ ||
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opcode == DPIO_OPCODE_REG_READ);
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bar = 0;
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be = 0xf;
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@ -27,14 +29,13 @@ static int vlv_punit_rw(uint32_t port, uint8_t opcode, uint8_t addr,
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if (*ptr & IOSF_SB_BUSY) {
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fprintf(stderr, "warning: pcode (%s) mailbox access failed\n",
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opcode == PUNIT_OPCODE_REG_READ ?
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"read" : "write");
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is_read ? "read" : "write");
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return -EAGAIN;
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}
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ptr = (volatile uint32_t*)((volatile char*)mmio + VLV_IOSF_ADDR);
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*ptr = addr;
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if (opcode == PUNIT_OPCODE_REG_WRITE) {
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if (!is_read) {
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ptr = (volatile uint32_t*)((volatile char*)mmio +
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VLV_IOSF_DATA);
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*ptr = *val;
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@ -54,7 +55,7 @@ static int vlv_punit_rw(uint32_t port, uint8_t opcode, uint8_t addr,
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return -ETIMEDOUT;
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}
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if (opcode == PUNIT_OPCODE_REG_READ) {
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if (is_read) {
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ptr = (volatile uint32_t*)((volatile char*)mmio +
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VLV_IOSF_DATA);
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*val = *ptr;
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@ -66,20 +67,33 @@ static int vlv_punit_rw(uint32_t port, uint8_t opcode, uint8_t addr,
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int intel_punit_read(uint8_t addr, uint32_t *val)
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{
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return vlv_punit_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ, addr, val);
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return vlv_sideband_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ, addr, val);
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}
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int intel_punit_write(uint8_t addr, uint32_t val)
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{
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return vlv_punit_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE, addr, &val);
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return vlv_sideband_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE, addr, &val);
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}
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int intel_nc_read(uint8_t addr, uint32_t *val)
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{
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return vlv_punit_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_READ, addr, val);
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return vlv_sideband_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_READ, addr, val);
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}
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int intel_nc_write(uint8_t addr, uint32_t val)
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{
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return vlv_punit_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_WRITE, addr, &val);
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return vlv_sideband_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_WRITE, addr, &val);
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}
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uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
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{
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uint32_t val;
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vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_READ, reg, &val);
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return val;
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}
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void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
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{
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vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_WRITE, reg, &val);
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}
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@ -3552,32 +3552,32 @@ typedef enum {
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#define SFUSE_STRAP_DDID_DETECTED (1<<0)
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/* Valleyview related items */
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#define VLV_DISPLAY_BASE 0x180000
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/* Valleyview DPIO registers */
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#define VLV_DISPLAY_BASE 0x180000
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#define DPIO_PKT 0x2100
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#define DPIO_RID (0 << 24)
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#define DPIO_OP_WRITE (1 << 16)
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#define DPIO_OP_READ (0 << 16)
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#define DPIO_PORTID (0x12 << 8)
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#define DPIO_BYTE (0xf << 4)
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#define DPIO_BUSY (1 << 0)
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#define DPIO_DATA 0x2104
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#define DPIO_REG 0x2108
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/* VLV IOSF access */
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#define VLV_IOSF_DOORBELL_REQ 0x182100
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/*
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* IOSF sideband
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*/
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#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
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#define IOSF_DEVFN_SHIFT 24
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#define IOSF_OPCODE_SHIFT 16
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#define IOSF_PORT_SHIFT 8
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#define IOSF_BYTE_ENABLES_SHIFT 4
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#define IOSF_BAR_SHIFT 1
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#define IOSF_SB_BUSY (1<<0)
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#define IOSF_PORT_BUNIT 0x3
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#define IOSF_PORT_PUNIT 0x4
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#define IOSF_PORT_NC 0x11
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#define VLV_IOSF_DATA 0x182104
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#define VLV_IOSF_ADDR 0x182108
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#define IOSF_PORT_DPIO 0x12
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#define IOSF_PORT_GPIO_NC 0x13
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#define IOSF_PORT_CCK 0x14
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#define IOSF_PORT_CCU 0xA9
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#define IOSF_PORT_GPS_CORE 0x48
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#define IOSF_PORT_FLISDSI 0x1B
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#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
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#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
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#define DPIO_OPCODE_REG_READ 0
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#define DPIO_OPCODE_REG_WRITE 1
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#define PUNIT_OPCODE_REG_READ 6
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#define PUNIT_OPCODE_REG_WRITE 7
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@ -12,7 +12,7 @@ I915ChipsetPython_la_SOURCES = chipset_wrap_python.c intel_chipset.c \
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$(top_srcdir)/lib/intel_pci.c \
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$(top_srcdir)/lib/intel_reg_map.c \
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$(top_srcdir)/lib/intel_mmio.c \
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$(top_srcdir)/lib/intel_dpio.c
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$(top_srcdir)/lib/intel_iosf.c
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chipset_wrap_python.c chipset.py: chipset.i
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$(AM_V_GEN)$(SWIG) $(AX_SWIG_PYTHON_OPT) -I/usr/include -I$(top_srcdir)/lib -o $@ $<
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