mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-08 08:26:10 +00:00
81095305f4
This makes it a bit more like the kernel, so we can go poke at DPIO and other IOSF regs a bit more easily. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
100 lines
2.3 KiB
C
100 lines
2.3 KiB
C
#include <unistd.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <err.h>
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#include <errno.h>
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#include "intel_gpu_tools.h"
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#define TIMEOUT_US 500000
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static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint8_t addr,
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uint32_t *val)
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{
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volatile uint32_t *ptr;
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int timeout = 0;
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uint32_t cmd, devfn, be, bar;
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int is_read = (opcode == PUNIT_OPCODE_REG_READ ||
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opcode == DPIO_OPCODE_REG_READ);
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bar = 0;
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be = 0xf;
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devfn = 16;
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cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
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(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
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(bar << IOSF_BAR_SHIFT);
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ptr = (volatile uint32_t*)((volatile char*)mmio +
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VLV_IOSF_DOORBELL_REQ);
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if (*ptr & IOSF_SB_BUSY) {
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fprintf(stderr, "warning: pcode (%s) mailbox access failed\n",
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is_read ? "read" : "write");
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return -EAGAIN;
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}
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ptr = (volatile uint32_t*)((volatile char*)mmio + VLV_IOSF_ADDR);
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*ptr = addr;
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if (!is_read) {
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ptr = (volatile uint32_t*)((volatile char*)mmio +
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VLV_IOSF_DATA);
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*ptr = *val;
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}
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ptr = (volatile uint32_t*)((volatile char*)mmio +
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VLV_IOSF_DOORBELL_REQ);
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*ptr = cmd;
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do {
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usleep(1);
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timeout++;
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} while ((*ptr & IOSF_SB_BUSY) && timeout < TIMEOUT_US);
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if (timeout >= TIMEOUT_US) {
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fprintf(stderr, "timeout waiting for pcode %s (%d) to finish\n",
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opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
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addr);
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return -ETIMEDOUT;
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}
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if (is_read) {
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ptr = (volatile uint32_t*)((volatile char*)mmio +
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VLV_IOSF_DATA);
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*val = *ptr;
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}
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*ptr = 0;
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return 0;
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}
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int intel_punit_read(uint8_t addr, uint32_t *val)
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{
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return vlv_sideband_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ, addr, val);
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}
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int intel_punit_write(uint8_t addr, uint32_t val)
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{
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return vlv_sideband_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE, addr, &val);
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}
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int intel_nc_read(uint8_t addr, uint32_t *val)
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{
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return vlv_sideband_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_READ, addr, val);
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}
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int intel_nc_write(uint8_t addr, uint32_t val)
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{
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return vlv_sideband_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_WRITE, addr, &val);
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}
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uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
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{
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uint32_t val;
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vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_READ, reg, &val);
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return val;
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}
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void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
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{
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vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_WRITE, reg, &val);
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}
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