mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2026-08-22 13:52:54 +00:00
Get the wm program to parse.
This commit is contained in:
Eric Anholt
committed by
Damien Lespiau
Damien Lespiau
parent
22a1063cc0
commit
6c98c8d578
+114
-39
@@ -59,9 +59,9 @@
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%token TYPE_UD, TYPE_D, TYPE_UW, TYPE_W, TYPE_UB, TYPE_B,
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%token TYPE_VF, TYPE_HF, TYPE_V, TYPE_F
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%token ALIGN1
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%token ALIGN1 ALIGN16 MASK_DISABLE EOT
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%token GENREGFILE MSGREGFILE
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%token GENREG MSGREG ACCREG ADDRESSREG FLAGREG CONTROLREG IPREG
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%token MOV
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%token MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2
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@@ -69,21 +69,26 @@
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%token SEND NULL_TOKEN MATH SAMPLER GATEWAY READ WRITE URB THREAD_SPAWNER
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%token MSGLEN RETURNLEN
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%token SATURATE
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%token <integer> INTEGER
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%token <number> NUMBER
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%type <instruction> instruction unaryinstruction binaryinstruction
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%type <instruction> binaryaccinstruction triinstruction sendinstruction
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%type <instruction> specialinstruction
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%type <instruction> dstoperand dstoperandex dstreg accreg
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%type <instruction> directsrcaccoperand src directsrcoperand srcimm
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%type <instruction> srcacc srcaccimm
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%type <instruction> instoptions instoption_list instoption
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%type <program> instrseq
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%type <integer> unaryop binaryop binaryaccop triop
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%type <integer> unaryop binaryop binaryaccop
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%type <integer> conditionalmodifier saturate
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%type <integer> regtype srcimmtype execsize dstregion
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%type <integer> gensubregnum msgsubregnum msgtarget
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%type <integer> subregnum msgtarget
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%type <region> region
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%type <direct_gen_reg> directgenreg directmsgreg
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%type <direct_gen_reg> directgenreg directmsgreg addrreg accreg flagreg maskreg
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%type <direct_gen_reg> nullreg
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%type <imm32> imm32
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%%
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@@ -126,12 +131,19 @@ instruction: unaryinstruction
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| binaryinstruction
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| binaryaccinstruction
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| triinstruction
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| specialinstruction
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;
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unaryinstruction: predicate unaryop execsize dst srcaccimm instoptions
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unaryinstruction:
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predicate unaryop conditionalmodifier saturate execsize
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dst srcaccimm instoptions
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{
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$$.header.opcode = $2;
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$$.header.execution_size = $3;
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$$.header.saturate = $3;
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$$.header.destreg__conditionalmod = $4;
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$$.header.execution_size = $5;
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$$.bits1 = $7.bits1;
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/* XXX: more */
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}
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;
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@@ -139,20 +151,28 @@ unaryop: MOV { $$ = BRW_OPCODE_MOV; }
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;
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binaryinstruction:
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predicate binaryop execsize dst src srcimm instoptions
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predicate binaryop conditionalmodifier saturate execsize
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dst src srcimm instoptions
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{
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$$.header.opcode = $2;
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$$.header.execution_size = $3;
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$$.header.saturate = $3;
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$$.header.destreg__conditionalmod = $4;
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$$.header.execution_size = $5;
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/* XXX: more */
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}
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;
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binaryop: MUL { $$ = BRW_OPCODE_MUL; }
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| MAC { $$ = BRW_OPCODE_MAC; }
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binaryaccinstruction:
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predicate binaryaccop execsize dst srcacc srcimm instoptions
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predicate binaryaccop conditionalmodifier saturate execsize
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dst srcacc srcimm instoptions
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{
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$$.header.opcode = $2;
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$$.header.execution_size = $3;
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$$.header.saturate = $3;
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$$.header.destreg__conditionalmod = $4;
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$$.header.execution_size = $5;
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}
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;
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@@ -162,20 +182,21 @@ binaryaccop: ADD { $$ = BRW_OPCODE_ADD; }
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triinstruction: sendinstruction
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/* XXX formatting of this instruction */
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sendinstruction: predicate SEND INTEGER execsize postdst curdst msgtarget
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sendinstruction: predicate SEND INTEGER execsize dst payload msgtarget
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MSGLEN INTEGER RETURNLEN INTEGER instoptions
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{
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$$.header.opcode = BRW_OPCODE_SEND;
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$$.header.execution_size = $4;
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$$.header.destreg__conditonalmod = $3;
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$$.header.destreg__conditionalmod = $3;
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}
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specialinstruction: NOP
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{
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$$.header.opcode = BRW_OPCODE_NOP;
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}
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/* XXX! */
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postdst: dstoperand
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;
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/* XXX! */
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curdst: directsrcoperand
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payload: directsrcoperand
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;
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msgtarget: NULL_TOKEN { $$ = BRW_MESSAGE_TARGET_NULL; }
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@@ -190,8 +211,7 @@ msgtarget: NULL_TOKEN { $$ = BRW_MESSAGE_TARGET_NULL; }
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/* 1.4.2: Destination register */
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/** XXX: dstoperandex */
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dst: dstoperand
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dst: dstoperand | dstoperandex
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/* XXX: dstregion writemask */
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dstoperand: dstreg dstregion regtype
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@@ -200,17 +220,31 @@ dstoperand: dstreg dstregion regtype
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* filled in.
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*/
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$$.bits1 = $1.bits1;
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$$.bits1.da1.dest_reg_type = $2;
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$$.bits1.da1.dest_reg_type = $2; /* XXX */
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/* XXX: $3 */
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}
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;
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dstoperandex: accreg dstregion regtype
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{
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/* Returns an instruction with just the destination register
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* filled in.
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*/
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$$.bits1 = $1.bits1;
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$$.bits1.da1.dest_reg_type = $2;
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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/* XXX: $2 $3 */
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}
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| nullreg
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{
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/* Returns an instruction with just the destination register
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* filled in.
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*/
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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}
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;
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/* XXX: indirectgenreg, directmsgreg, indirectmsgreg */
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dstreg: directgenreg
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@@ -288,18 +322,7 @@ directsrcoperand: directgenreg region regtype
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}
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;
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/* 1.4.5: Register files and register numbers */
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directgenreg: GENREGFILE INTEGER gensubregnum
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{
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/* Returns an instruction with just the destination register
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* fields filled in.
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*/
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$$.reg_file = BRW_GENERAL_REGISTER_FILE;
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$$.reg_nr = $2;
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$$.subreg_nr = $3;
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}
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gensubregnum: DOT INTEGER
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subregnum: DOT INTEGER
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{
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$$ = $2;
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}
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@@ -310,7 +333,18 @@ gensubregnum: DOT INTEGER
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}
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;
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directmsgreg: MSGREGFILE INTEGER msgsubregnum
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/* 1.4.5: Register files and register numbers */
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directgenreg: GENREG INTEGER subregnum
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{
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/* Returns an instruction with just the destination register
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* fields filled in.
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*/
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$$.reg_file = BRW_GENERAL_REGISTER_FILE;
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$$.reg_nr = $2;
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$$.subreg_nr = $3;
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}
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directmsgreg: MSGREG INTEGER subregnum
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{
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/* Returns an instruction with just the destination register
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* fields filled in.
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@@ -321,7 +355,34 @@ directmsgreg: MSGREGFILE INTEGER msgsubregnum
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}
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;
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msgsubregnum: gensubregnum
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accreg: ACCREG INTEGER subregnum
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{
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/* Returns an instruction with just the destination register
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* fields filled in.
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*/
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$$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
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$$.reg_nr = BRW_ARF_ACCUMULATOR | $2;
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$$.subreg_nr = $3;
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}
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;
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addrreg: ADDRESSREG INTEGER subregnum
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{
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/* Returns an instruction with just the destination register
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* fields filled in.
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*/
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$$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
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$$.reg_nr = BRW_ARF_ADDRESS | $2;
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$$.subreg_nr = $3;
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}
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;
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nullreg: NULL_TOKEN
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{
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$$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
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$$.reg_nr = BRW_ARF_NULL;
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$$.subreg_nr = 0;
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}
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;
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/* 1.4.7: Regions */
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@@ -382,14 +443,28 @@ execsize: LPAREN INTEGER RPAREN
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}
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;
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saturate: /* empty */ { $$ = 0; }
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| DOT SATURATE { $$ = 1; }
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;
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conditionalmodifier:
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;
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/* 1.4.13: Instruction options */
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/* XXX: this is a comma-separated list, really. */
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instoptions: LCURLY instoption RCURLY
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instoptions: LCURLY instoption_list RCURLY
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{ $$ = $2; }
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;
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instoption_list: instoption instoption_list
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;
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/* XXX: fill me in. alignctrl, comprctrl, threadctrl, depctrl, maskctrl,
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* debugctrl, sendctrl
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*/
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instoption: ALIGN1
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instoption: ALIGN1 | ALIGN16 | MASK_DISABLE | EOT
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;
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%%
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extern int yylineno;
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