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assembler: Add support for D and UD in 3-src instructions
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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@@ -785,6 +785,11 @@ enum opcode {
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#define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */
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#define BRW_REGISTER_TYPE_F 7
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#define BRW_REGISTER_3SRC_TYPE_F 0
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#define BRW_REGISTER_3SRC_TYPE_D 1
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#define BRW_REGISTER_3SRC_TYPE_UD 2
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#define BRW_REGISTER_3SRC_TYPE_DF 3
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#define BRW_ARF_NULL 0x00
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#define BRW_ARF_ADDRESS 0x10
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#define BRW_ARF_ACCUMULATOR 0x20
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