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https://github.com/tiagovignatti/intel-gpu-tools.git
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quick_dump: SWIG chipset interface
This isn't strictly necessary it would have been easy enough to simply convert intel_chipset.h but this should be nice prep work for directly doing MMIO. It also serves as a nice review point. It's demonstrated with an autodetect function in the script. That autodetect has a hardcoded path that shouldn't be there, but it will go away in the next patch when we can properly link in libpciaccess. Thanks to Matt for helping whip the automake stuff into shape. v2: Switch to $(top_srcdir) Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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@@ -1,4 +1,4 @@
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DIST_SUBDIRS = quick_dump
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SUBDIRS = quick_dump
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bin_PROGRAMS = \
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intel_disable_clock_gating \
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@@ -1,6 +1,23 @@
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BUILT_SOURCES = chipset_wrap_python.c
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bin_SCRIPTS = quick_dump.py chipset.py
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lib_LTLIBRARIES = I915ChipsetPython.la
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I915ChipsetPython_la_CFLAGS = -I$(top_srcdir)/lib $(PYTHON_CPPFLAGS)
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I915ChipsetPython_la_LDFLAGS = -module -avoid-version $(PYTHON_LDFLAGS)
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I915ChipsetPython_la_SOURCES = chipset_wrap_python.c intel_chipset.c
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chipset_wrap_python.c: chipset.i
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$(SWIG) $(AX_SWIG_PYTHON_OPT) -I$(top_srcdir)/lib -o $@ $<
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all-local: I915ChipsetPython.la
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$(LN_S) -f .libs/I915ChipsetPython.so _chipset.so
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CLEANFILES = chipset_wrap_python.c chipset.py _chipset.so
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EXTRA_DIST = \
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base_display.txt base_interrupt.txt base_other.txt base_power.txt base_rings.txt \
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gen6_other.txt sandybridge \
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gen7_other.txt ivybridge \
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vlv_display.txt valleyview \
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quick_dump.py
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quick_dump.py \
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chipset.i chipset.py
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@@ -0,0 +1,12 @@
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%module chipset
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%{
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#include "intel_chipset.h"
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extern int is_sandybridge(unsigned short pciid);
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extern int is_ivybridge(unsigned short pciid);
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extern int is_valleyview(unsigned short pciid);
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%}
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%include "intel_chipset.h"
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extern int is_sandybridge(unsigned short pciid);
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extern int is_ivybridge(unsigned short pciid);
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extern int is_valleyview(unsigned short pciid);
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@@ -0,0 +1,16 @@
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#include "intel_chipset.h"
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int is_sandybridge(unsigned short pciid)
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{
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return IS_GEN6(pciid);
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}
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int is_ivybridge(unsigned short pciid)
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{
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return IS_IVYBRIDGE(pciid);
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}
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int is_valleyview(unsigned short pciid)
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{
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return IS_VALLEYVIEW(pciid);
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}
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@@ -5,6 +5,7 @@ import os
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import sys
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import ast
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import subprocess
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import chipset
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def parse_file(file):
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for line in file:
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@@ -18,6 +19,7 @@ def parse_file(file):
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parser = argparse.ArgumentParser(description='Dumb register dumper.')
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parser.add_argument('-b', '--baseless', action='store_true', default=False, help='baseless mode, ignore files starting with base_')
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parser.add_argument('-a', '--autodetect', action='store_true', default=False, help='autodetect chipset')
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parser.add_argument('profile', nargs='?', type=argparse.FileType('r'), default=None)
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args = parser.parse_args()
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@@ -29,6 +31,19 @@ if args.baseless == False:
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file = open(name.rstrip(), 'r')
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parse_file(file)
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if args.autodetect:
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sysfs_file = open('/sys/class/drm/card0/device/device', 'r')
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devid_str = sysfs_file.read()
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devid = int(devid_str, 16)
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if chipset.is_sandybridge(devid):
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args.profile = open('sandybridge', 'r')
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elif chipset.is_ivybridge(devid):
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args.profile = open('ivybridge', 'r')
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elif chipset.is_valleyview(devid):
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args.profile = open('valleyview', 'r')
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else:
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print("Autodetect of %x " + devid + " failed")
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if args.profile == None:
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sys.exit()
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