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igt/gem_exec_reloc: Exercise updating relocations of an active object

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Supersedes gem_dummy_reloc_loop.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2016-03-14 13:59:18 +00:00
parent e5abd779cf
commit 5acda10e7f
3 changed files with 108 additions and 313 deletions
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1
tests/Makefile.sources
View File

@ -27,7 +27,6 @@ TESTS_progs_M = \
gem_ctx_param_basic \
gem_ctx_bad_exec \
gem_ctx_exec \
gem_dummy_reloc_loop \
gem_eio \
gem_evict_alignment \
gem_evict_everything \

312
tests/gem_dummy_reloc_loop.c
View File

@ -1,312 +0,0 @@
/*
* Copyright © 2011 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
*
*/
#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
#include "drm.h"
#include "intel_bufmgr.h"
#include "i830_reg.h"
#define LOCAL_I915_EXEC_VEBOX (4<<0)
#define LOCAL_I915_EXEC_BSD_RING1 (1<<13)
#define LOCAL_I915_EXEC_BSD_RING2 (2<<13)
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static drm_intel_bo *target_buffer;
#define NUM_FD 50
static int mfd[NUM_FD];
static drm_intel_bufmgr *mbufmgr[NUM_FD];
static struct intel_batchbuffer *mbatch[NUM_FD];
static drm_intel_bo *mbuffer[NUM_FD];
/*
* Testcase: Basic check of ring<->cpu sync using a dummy reloc
*
* The last test (that randomly switches the ring) seems to be pretty effective
* at hitting the missed irq bug that's worked around with the HWSTAM irq write.
*/
IGT_TEST_DESCRIPTION("Check ring<->cpu sync using a dummy reloc.");
#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
#define MI_DO_COMPARE (1<<21)
static void
dummy_reloc_loop(int ring)
{
int i;
for (i = 0; i < 0x100000; i++) {
BEGIN_BATCH(4, 1);
if (ring == I915_EXEC_RENDER) {
OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
OUT_BATCH(0xffffffff); /* compare dword */
OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(MI_NOOP);
} else {
OUT_BATCH(MI_FLUSH_DW | 1);
OUT_BATCH(0); /* reserved */
OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
}
ADVANCE_BATCH();
intel_batchbuffer_flush_on_ring(batch, ring);
drm_intel_bo_map(target_buffer, 0);
// map to force completion
drm_intel_bo_unmap(target_buffer);
}
}
static void
dummy_reloc_loop_random_ring(int num_rings)
{
int i;
srandom(0xdeadbeef);
for (i = 0; i < 0x100000; i++) {
int ring = random() % num_rings + 1;
BEGIN_BATCH(4, 1);
if (ring == I915_EXEC_RENDER) {
OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
OUT_BATCH(0xffffffff); /* compare dword */
OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(MI_NOOP);
} else {
OUT_BATCH(MI_FLUSH_DW | 1);
OUT_BATCH(0); /* reserved */
OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
}
ADVANCE_BATCH();
intel_batchbuffer_flush_on_ring(batch, ring);
drm_intel_bo_map(target_buffer, 0);
// map to force waiting on rendering
drm_intel_bo_unmap(target_buffer);
}
}
static void
dummy_reloc_loop_random_ring_multi_fd(int num_rings)
{
int i;
struct intel_batchbuffer *saved_batch;
saved_batch = batch;
srandom(0xdeadbeef);
for (i = 0; i < 0x100000; i++) {
int mindex;
int ring = random() % num_rings + 1;
mindex = random() % NUM_FD;
batch = mbatch[mindex];
BEGIN_BATCH(4, 1);
if (ring == I915_EXEC_RENDER) {
OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
OUT_BATCH(0xffffffff); /* compare dword */
OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(MI_NOOP);
} else {
OUT_BATCH(MI_FLUSH_DW | 1);
OUT_BATCH(0); /* reserved */
OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
}
ADVANCE_BATCH();
intel_batchbuffer_flush_on_ring(batch, ring);
drm_intel_bo_map(target_buffer, 0);
// map to force waiting on rendering
drm_intel_bo_unmap(target_buffer);
}
batch = saved_batch;
}
int fd;
int devid;
int num_rings;
igt_main
{
igt_skip_on_simulation();
igt_fixture {
int i;
fd = drm_open_driver(DRIVER_INTEL);
devid = intel_get_drm_devid(fd);
num_rings = gem_get_num_rings(fd);
/* Not yet implemented on pre-snb. */
igt_require(HAS_BLT_RING(devid));
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
igt_assert(bufmgr);
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
batch = intel_batchbuffer_alloc(bufmgr, devid);
igt_assert(batch);
target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
igt_assert(target_buffer);
/* Create multi drm_fd and map one gem object to multi gem_contexts */
{
unsigned int target_flink;
char buffer_name[32];
igt_assert(dri_bo_flink(target_buffer, &target_flink) == 0);
for (i = 0; i < NUM_FD; i++) {
sprintf(buffer_name, "Target buffer %d\n", i);
mfd[i] = drm_open_driver(DRIVER_INTEL);
mbufmgr[i] = drm_intel_bufmgr_gem_init(mfd[i], 4096);
igt_assert_f(mbufmgr[i],
"fail to initialize buf manager "
"for drm_fd %d\n",
mfd[i]);
drm_intel_bufmgr_gem_enable_reuse(mbufmgr[i]);
mbatch[i] = intel_batchbuffer_alloc(mbufmgr[i], devid);
igt_assert_f(mbatch[i],
"fail to create batchbuffer "
"for drm_fd %d\n",
mfd[i]);
mbuffer[i] = intel_bo_gem_create_from_name(
mbufmgr[i],
buffer_name,
target_flink);
igt_assert_f(mbuffer[i],
"fail to create gem bo from global "
"gem_handle %d for drm_fd %d\n",
target_flink, mfd[i]);
}
}
}
igt_subtest("render") {
igt_info("running dummy loop on render\n");
dummy_reloc_loop(I915_EXEC_RENDER);
igt_info("dummy loop run on render completed\n");
}
igt_subtest("bsd") {
gem_require_ring(fd, I915_EXEC_BSD);
sleep(2);
igt_info("running dummy loop on bsd\n");
dummy_reloc_loop(I915_EXEC_BSD);
igt_info("dummy loop run on bsd completed\n");
}
igt_subtest("blt") {
gem_require_ring(fd, I915_EXEC_BLT);
sleep(2);
igt_info("running dummy loop on blt\n");
dummy_reloc_loop(I915_EXEC_BLT);
igt_info("dummy loop run on blt completed\n");
}
#ifdef I915_EXEC_VEBOX
igt_subtest("vebox") {
gem_require_ring(fd, I915_EXEC_VEBOX);
sleep(2);
igt_info("running dummy loop on vebox\n");
dummy_reloc_loop(LOCAL_I915_EXEC_VEBOX);
igt_info("dummy loop run on vebox completed\n");
}
#endif
igt_subtest("bsd-ring1") {
igt_require(gem_has_bsd2(fd));
sleep(2);
igt_info("running dummy loop on bsd-ring1\n");
dummy_reloc_loop(I915_EXEC_BSD|LOCAL_I915_EXEC_BSD_RING1);
igt_info("dummy loop run on bsd-ring1 completed\n");
}
igt_subtest("bsd-ring2") {
igt_require(gem_has_bsd2(fd));
sleep(2);
igt_info("running dummy loop on bsd-ring2\n");
dummy_reloc_loop(I915_EXEC_BSD|LOCAL_I915_EXEC_BSD_RING2);
igt_info("dummy loop run on bsd-ring2 completed\n");
}
igt_subtest("mixed") {
if (num_rings > 1) {
sleep(2);
igt_info("running dummy loop on random rings\n");
dummy_reloc_loop_random_ring(num_rings);
igt_info("dummy loop run on random rings completed\n");
}
}
igt_subtest("mixed_multi_fd") {
if (num_rings > 1) {
sleep(2);
igt_info("running dummy loop on random rings based on "
"multi drm_fd\n");
dummy_reloc_loop_random_ring_multi_fd(num_rings);
igt_info("dummy loop run on random rings based on "
"multi drm_fd completed\n");
}
}
igt_fixture {
int i;
/* Free the buffer/batchbuffer/buffer mgr for multi-fd */
{
for (i = 0; i < NUM_FD; i++) {
dri_bo_unreference(mbuffer[i]);
intel_batchbuffer_free(mbatch[i]);
drm_intel_bufmgr_destroy(mbufmgr[i]);
close(mfd[i]);
}
}
drm_intel_bo_unreference(target_buffer);
intel_batchbuffer_free(batch);
drm_intel_bufmgr_destroy(bufmgr);
close(fd);
}
}

108
tests/gem_exec_reloc.c
View File

@ -25,6 +25,11 @@
IGT_TEST_DESCRIPTION("Basic sanity check of execbuf-ioctl relocations.");
#define LOCAL_I915_EXEC_BSD_SHIFT (13)
#define LOCAL_I915_EXEC_BSD_MASK (3 << LOCAL_I915_EXEC_BSD_SHIFT)
#define ENGINE_MASK (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
static uint32_t find_last_set(uint64_t x)
{
uint32_t i = 0;
@ -215,6 +220,102 @@ static void from_gpu(int fd)
munmap(relocs, 4096);
}
static bool ignore_engine(int gen, unsigned engine)
{
return gen == 6 && (engine & ~(3<<13)) == I915_EXEC_BSD;
}
static void check_bo(int fd, uint32_t handle)
{
uint32_t *map;
int i;
igt_debug("Verifying result\n");
map = gem_mmap__cpu(fd, handle, 0, 4096, PROT_READ);
gem_set_domain(fd, handle, I915_GEM_DOMAIN_CPU, 0);
for (i = 0; i < 1024; i++)
igt_assert_eq(map[i], i);
munmap(map, 4096);
}
static void active(int fd, unsigned engine)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_relocation_entry reloc;
struct drm_i915_gem_exec_object2 obj[2];
struct drm_i915_gem_execbuffer2 execbuf;
unsigned engines[16];
unsigned nengine;
int pass;
nengine = 0;
if (engine == -1) {
for_each_engine(fd, engine) {
if (!ignore_engine(gen, engine))
engines[nengine++] = engine;
}
} else {
igt_require(gem_has_ring(fd, engine));
igt_require(!ignore_engine(gen, engine));
engines[nengine++] = engine;
}
igt_require(nengine);
memset(obj, 0, sizeof(obj));
obj[0].handle = gem_create(fd, 4096);
obj[1].handle = gem_create(fd, 64*1024);
obj[1].relocs_ptr = (uintptr_t)&reloc;
obj[1].relocation_count = 1;
memset(&reloc, 0, sizeof(reloc));
reloc.offset = sizeof(uint32_t);
reloc.target_handle = obj[0].handle;
if (gen < 8 && gen >= 4)
reloc.offset += sizeof(uint32_t);
reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = (uintptr_t)obj;
execbuf.buffer_count = 2;
if (gen < 6)
execbuf.flags |= I915_EXEC_SECURE;
for (pass = 0; pass < 1024; pass++) {
uint32_t batch[16];
int i = 0;
batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
if (gen >= 8) {
batch[++i] = 0;
batch[++i] = 0;
} else if (gen >= 4) {
batch[++i] = 0;
batch[++i] = 0;
} else {
batch[i]--;
batch[++i] = 0;
}
batch[++i] = pass;
batch[++i] = MI_BATCH_BUFFER_END;
gem_write(fd, obj[1].handle, pass*sizeof(batch),
batch, sizeof(batch));
}
for (pass = 0; pass < 1024; pass++) {
reloc.delta = 4*pass;
reloc.presumed_offset = -1;
execbuf.flags &= ~ENGINE_MASK;
execbuf.flags |= engines[rand() % nengine];
gem_execbuf(fd, &execbuf);
execbuf.batch_start_offset += 64;
reloc.offset += 64;
}
gem_close(fd, obj[1].handle);
check_bo(fd, obj[0].handle);
gem_close(fd, obj[0].handle);
}
igt_main
{
uint64_t size;
@ -237,6 +338,13 @@ igt_main
igt_subtest("gpu")
from_gpu(fd);
igt_subtest("active")
active(fd, -1);
for (const struct intel_execution_engine *e = intel_execution_engines;
e->name; e++) {
igt_subtest_f("active-%s", e->name)
active(fd, e->exec_id | e->flags);
}
igt_fixture
close(fd);
}