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https://github.com/tiagovignatti/intel-gpu-tools.git
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tests/gem_ring_sync_loop: Exercise all rings
Fix the engine selection to exercise all possible rings and in doing so completely obsoletes gem_multi_bsd_sync_loop. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson
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3d9bcd0804
commit
e5abd779cf
@ -156,7 +156,6 @@ TESTS_progs = \
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gem_render_tiled_blits \
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gem_ring_sync_copy \
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gem_ring_sync_loop \
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gem_multi_bsd_sync_loop \
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gem_seqno_wrap \
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gem_set_tiling_vs_gtt \
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gem_set_tiling_vs_pwrite \
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@ -1,162 +0,0 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_ring_sync_loop_*.c)
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* Zhao Yakui <yakui.zhao@intel.com>
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*
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*/
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#include "igt.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include "drm.h"
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#include "intel_bufmgr.h"
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#include "i830_reg.h"
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IGT_TEST_DESCRIPTION("Basic check of ring<->ring sync using a dummy reloc.");
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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static drm_intel_bo *target_buffer;
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#define NUM_FD 50
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static int mfd[NUM_FD];
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static drm_intel_bufmgr *mbufmgr[NUM_FD];
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static struct intel_batchbuffer *mbatch[NUM_FD];
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static drm_intel_bo *mbuffer[NUM_FD];
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/*
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* Testcase: Basic check of ring<->ring sync using a dummy reloc
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*
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* Extremely efficient at catching missed irqs with semaphores=0 ...
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*/
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#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
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#define MI_DO_COMPARE (1<<21)
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static void
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store_dword_loop(int fd)
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{
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int i;
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int num_rings = gem_get_num_rings(fd);
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srandom(0xdeadbeef);
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for (i = 0; i < SLOW_QUICK(0x100000, 10); i++) {
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int ring, mindex;
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ring = random() % num_rings + 1;
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mindex = random() % NUM_FD;
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batch = mbatch[mindex];
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if (ring == I915_EXEC_RENDER) {
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BEGIN_BATCH(4, 1);
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OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
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OUT_BATCH(0xffffffff); /* compare dword */
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OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(MI_NOOP);
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ADVANCE_BATCH();
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} else {
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BEGIN_BATCH(4, 1);
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OUT_BATCH(MI_FLUSH_DW | 1);
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OUT_BATCH(0); /* reserved */
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OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
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ADVANCE_BATCH();
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}
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intel_batchbuffer_flush_on_ring(batch, ring);
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}
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drm_intel_bo_map(target_buffer, 0);
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// map to force waiting on rendering
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drm_intel_bo_unmap(target_buffer);
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}
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igt_simple_main
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{
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int fd;
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int devid;
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int i;
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fd = drm_open_driver(DRIVER_INTEL);
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devid = intel_get_drm_devid(fd);
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gem_require_ring(fd, I915_EXEC_BLT);
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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igt_assert_f(bufmgr, "fail to initialize the buf manager\n");
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drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
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igt_assert_f(target_buffer, "fail to create the gem bo\n");
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/* Create multiple drm_fd and map one gem_object among multi drm_fd */
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{
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unsigned int target_flink;
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char buffer_name[32];
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igt_assert(dri_bo_flink(target_buffer, &target_flink) == 0);
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for (i = 0; i < NUM_FD; i++) {
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sprintf(buffer_name, "Target buffer %d\n", i);
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mfd[i] = drm_open_driver(DRIVER_INTEL);
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mbufmgr[i] = drm_intel_bufmgr_gem_init(mfd[i], 4096);
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igt_assert_f(mbufmgr[i],
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"fail to initialize buf manager for drm_fd %d\n",
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mfd[i]);
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drm_intel_bufmgr_gem_enable_reuse(mbufmgr[i]);
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mbatch[i] = intel_batchbuffer_alloc(mbufmgr[i], devid);
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igt_assert_f(mbatch[i],
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"fail to create batchbuffer for drm_fd %d\n",
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mfd[i]);
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mbuffer[i] = intel_bo_gem_create_from_name(mbufmgr[i], buffer_name, target_flink);
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igt_assert_f(mbuffer[i],
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"fail to create buffer bo from global "
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"gem handle %d for drm_fd %d\n",
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target_flink, mfd[i]);
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}
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}
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store_dword_loop(fd);
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{
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for (i = 0; i < NUM_FD; i++) {
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dri_bo_unreference(mbuffer[i]);
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intel_batchbuffer_free(mbatch[i]);
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drm_intel_bufmgr_destroy(mbufmgr[i]);
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close(mfd[i]);
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}
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}
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drm_intel_bo_unreference(target_buffer);
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drm_intel_bufmgr_destroy(bufmgr);
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close(fd);
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}
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@ -39,12 +39,19 @@ static void
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sync_loop(int fd)
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{
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const uint32_t bbe = MI_BATCH_BUFFER_END;
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int num_rings = gem_get_num_rings(fd);
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 object[2];
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struct drm_i915_gem_relocation_entry reloc[1];
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unsigned engines[16];
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unsigned nengine;
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unsigned engine;
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int i;
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nengine = 0;
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for_each_engine(fd, engine)
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engines[nengine++] = engine;
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igt_require(nengine);
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memset(object, 0, sizeof(object));
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object[0].handle = gem_create(fd, 4096);
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object[0].flags = EXEC_OBJECT_WRITE;
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@ -74,7 +81,7 @@ sync_loop(int fd)
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srandom(0xdeadbeef);
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for (i = 0; i < SLOW_QUICK(0x100000, 10); i++) {
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execbuf.flags = random() % num_rings + 1;
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execbuf.flags = engines[rand() % nengine];
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gem_execbuf(fd, &execbuf);
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}
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@ -88,7 +95,6 @@ igt_simple_main
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int fd;
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fd = drm_open_driver(DRIVER_INTEL);
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igt_require(gem_get_num_rings(fd) > 1);
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intel_detect_and_clear_missed_interrupts(fd);
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sync_loop(fd);
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