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intel_bios_reader: Add support to dump MIPI Configuration Block #52

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Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Gaurav K Singh
2014-07-16 19:39:32 +05:30
committed by Damien Lespiau
parent ff6b068ecd
commit 525044ba32
2 changed files with 226 additions and 0 deletions
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tools/intel_bios.h
+132
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@@ -85,6 +85,8 @@ struct bdb_header {
#define BDB_LVDS_LFP_DATA 42
#define BDB_LVDS_BACKLIGHT 43
#define BDB_LVDS_POWER 44
#define BDB_MIPI_CONFIG 52
#define BDB_MIPI_SEQUENCE 53
#define BDB_SKIP 254 /* VBIOS private block, ignore */
struct bdb_general_features {
@@ -597,6 +599,136 @@ struct bdb_edp {
uint16_t edp_t3_optimization;
} __attribute__ ((packed));
/* Block 52 contains MiPi Panel info
* 6 such enteries will there. Index into correct
* entery is based on the panel_index in #40 LFP
*/
#define MAX_MIPI_CONFIGURATIONS 6
struct mipi_config {
uint16_t panel_id;
/* General Params */
uint32_t dithering:1;
uint32_t rsvd1:1;
uint32_t panel_type:1;
uint32_t panel_arch_type:2;
uint32_t cmd_mode:1;
uint32_t vtm:2;
uint32_t cabc:1;
uint32_t pwm_blc:1;
/* Bit 13:10
* 000 - Reserved, 001 - RGB565, 002 - RGB666,
* 011 - RGB666Loosely packed, 100 - RGB888,
* others - rsvd
*/
uint32_t videomode_color_format:4;
/* Bit 15:14
* 0 - No rotation, 1 - 90 degree
* 2 - 180 degree, 3 - 270 degree
*/
uint32_t rotation:2;
uint32_t bta:1;
uint32_t rsvd2:15;
/* 2 byte Port Description */
uint16_t dual_link:2;
uint16_t lane_cnt:2;
uint16_t rsvd3:12;
/* 2 byte DSI COntroller params */
/* 0 - Using DSI PHY, 1 - TE usage */
uint16_t dsi_usage:1;
uint16_t rsvd4:15;
uint8_t rsvd5[5];
uint32_t dsi_ddr_clk;
uint32_t bridge_ref_clk;
uint8_t byte_clk_sel:2;
uint8_t rsvd6:6;
/* DPHY Flags */
uint16_t dphy_param_valid:1;
uint16_t eot_disabled:1;
uint16_t clk_stop:1;
uint16_t rsvd7:13;
uint32_t hs_tx_timeout;
uint32_t lp_rx_timeout;
uint32_t turn_around_timeout;
uint32_t device_reset_timer;
uint32_t master_init_timer;
uint32_t dbi_bw_timer;
uint32_t lp_byte_clk_val;
/* 4 byte Dphy Params */
uint32_t prepare_cnt:6;
uint32_t rsvd8:2;
uint32_t clk_zero_cnt:8;
uint32_t trail_cnt:5;
uint32_t rsvd9:3;
uint32_t exit_zero_cnt:6;
uint32_t rsvd10:2;
uint32_t clk_lane_switch_cnt;
uint32_t hl_switch_cnt;
uint32_t rsvd11[6];
/* timings based on dphy spec */
uint8_t tclk_miss;
uint8_t tclk_post;
uint8_t rsvd12;
uint8_t tclk_pre;
uint8_t tclk_prepare;
uint8_t tclk_settle;
uint8_t tclk_term_enable;
uint8_t tclk_trail;
uint16_t tclk_prepare_clkzero;
uint8_t rsvd13;
uint8_t td_term_enable;
uint8_t teot;
uint8_t ths_exit;
uint8_t ths_prepare;
uint16_t ths_prepare_hszero;
uint8_t rsvd14;
uint8_t ths_settle;
uint8_t ths_skip;
uint8_t ths_trail;
uint8_t tinit;
uint8_t tlpx;
uint8_t rsvd15[3];
/* GPIOs */
uint8_t panel_enable;
uint8_t bl_enable;
uint8_t pwm_enable;
uint8_t reset_r_n;
uint8_t pwr_down_r;
uint8_t stdby_r_n;
} __attribute__ ((packed));
/* Block 52 contains MiPi configuration block
* 6 * bdb_mipi_config, followed by 6 pps data
* block below
*/
struct mipi_pps_data {
uint16_t panel_on_delay;
uint16_t bl_enable_delay;
uint16_t bl_disable_delay;
uint16_t panel_off_delay;
uint16_t panel_power_cycle_delay;
} __attribute__ ((packed));
struct bdb_mipi_config {
struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
} __attribute__ ((packed));
/*
* Driver<->VBIOS interaction occurs through scratch bits in
* GR18 & SWF*.