Search for the first Intel dri device.

This is vital in a multi-GPU system so that we only test the Intel card
and not the discrete GPUs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

lib/drmtest.c

@@ -29,6 +29,23 @@
 #include <sys/stat.h>
 #include <sys/ioctl.h>
 #include "drmtest.h"
+#include "i915_drm.h"
+#include "intel_chipset.h"
+
+static int
+is_intel(int fd)
+{
+	struct drm_i915_getparam gp;
+	int devid;
+
+	gp.param = I915_PARAM_CHIPSET_ID;
+	gp.value = &devid;
+
+	if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)))
+		return 0;
+
+	return IS_INTEL(devid);
+}
 
 /** Open the first DRM device we can find, searching up to 16 device nodes */
 int drm_open_any(void)
@@ -39,8 +56,13 @@ int drm_open_any(void)
 	for (i = 0; i < 16; i++) {
 		sprintf(name, "/dev/dri/card%d", i);
 		fd = open(name, O_RDWR);
-		if (fd != -1)
+		if (fd == -1)
+			continue;
+
+		if (is_intel(fd))
 			return fd;
+
+		close(fd);
 	}
 	abort();
 }
@@ -63,6 +85,11 @@ int drm_open_any_master(void)
 		if (fd == -1)
 			continue;
 
+		if (!is_intel(fd)) {
+			close(fd);
+			continue;
+		}
+
 		/* Check that we're the only opener and authed. */
 		client.idx = 0;
 		ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client);

lib/instdone.c

@@ -205,7 +205,7 @@ init_instdone_definitions(uint32_t devid)
 		gen6_instdone2_bit(GEN6_GS_DONE, "GS");
 		gen6_instdone2_bit(GEN6_VS0_DONE, "VS0");
 		gen6_instdone2_bit(GEN6_VF_DONE, "VF");
-	} else if (IS_IRONLAKE(devid)) {
+	} else if (IS_GEN5(devid)) {
 		gen4_instdone_bit(ILK_ROW_0_EU_0_DONE, "Row 0, EU 0");
 		gen4_instdone_bit(ILK_ROW_0_EU_1_DONE, "Row 0, EU 1");
 		gen4_instdone_bit(ILK_ROW_0_EU_2_DONE, "Row 0, EU 2");

lib/intel_chipset.h

@@ -95,7 +95,6 @@
 
 #define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
 #define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
-#define IS_IRONLAKE(devid)      (IS_ILD(devid) || IS_ILM(devid))
 
 #define IS_915(devid)		(devid == PCI_CHIP_I915_G || \
 				 devid == PCI_CHIP_E7221_G || \
@@ -111,6 +110,13 @@
 				 devid == PCI_CHIP_Q33_G || \
 				 devid == PCI_CHIP_Q35_G || IS_IGD(devid))
 
+#define IS_GEN2(devid)		(devid == PCI_CHIP_I830_M || \
+				 devid == PCI_CHIP_845_G || \
+				 devid == PCI_CHIP_I855_GM || \
+				 devid == PCI_CHIP_I865_G)
+
+#define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
+
 #define IS_GEN4(devid)		(devid == PCI_CHIP_I965_G || \
 				 devid == PCI_CHIP_I965_Q || \
 				 devid == PCI_CHIP_I965_G_1 || \
@@ -120,9 +126,11 @@
 				 IS_G4X(devid))
 
 #define IS_965(devid)		(IS_GEN4(devid) || \
-				 IS_IRONLAKE(devid) || \
+				 IS_GEN5(devid) || \
 				 IS_GEN6(devid))
 
+#define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
+
 #define IS_GEN6(devid)		(devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
 				 devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
 				 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
@@ -131,9 +139,16 @@
 				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
 				 devid == PCI_CHIP_SANDYBRIDGE_S)
 
-#define IS_9XX(devid)		(IS_915(devid) || \
-				 IS_945(devid) || \
-				 IS_965(devid))
-
-#define HAS_PCH_SPLIT(devid)	(IS_IRONLAKE(devid) ||	\
+#define IS_9XX(devid)		(IS_GEN3(devid) || \
+				 IS_GEN4(devid) || \
+				 IS_GEN4(devid) || \
+				 IS_GEN6(devid))
+
+#define IS_INTEL(devid)		(IS_GEN2(devid) || \
+				 IS_GEN3(devid) || \
+				 IS_GEN4(devid) || \
+				 IS_GEN4(devid) || \
+				 IS_GEN6(devid))
+
+#define HAS_PCH_SPLIT(devid)	(IS_GEN5(devid) ||	\
 				 IS_GEN6(devid))