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assembler: Remove trailing white space

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Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Damien Lespiau
2013-02-01 14:54:46 +00:00
parent 2f502bcaaa
commit 2d8b92a24b
7 changed files with 55 additions and 55 deletions
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assembler/brw_eu_emit.c
+24 -24
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@@ -2,7 +2,7 @@
Copyright (C) Intel Corp. 2006. All Rights Reserved.
Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
develop this 3D driver.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
@@ -10,11 +10,11 @@
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
@@ -22,13 +22,13 @@
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**********************************************************************/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*/
#include <string.h>
#include "brw_context.h"
@@ -115,7 +115,7 @@ brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
insn->bits1.da1.dest_reg_type = dest.type;
insn->bits1.da1.dest_address_mode = dest.address_mode;
if (dest.address_mode == BRW_ADDRESS_DIRECT) {
if (dest.address_mode == BRW_ADDRESS_DIRECT) {
insn->bits1.da1.dest_reg_nr = dest.nr;
if (insn->header.access_mode == BRW_ALIGN_1) {
@@ -276,7 +276,7 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
if (reg.file == BRW_IMMEDIATE_VALUE) {
insn->bits3.ud = reg.dw1.ud;
/* Required to set some fields in src1 as well:
*/
@@ -288,7 +288,7 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
insn->bits1.da1.src1_reg_type = reg.type;
*/
}
else
else
{
if (reg.address_mode == BRW_ADDRESS_DIRECT) {
if (insn->header.access_mode == BRW_ALIGN_1) {
@@ -304,7 +304,7 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
insn->bits2.ia1.src0_subreg_nr = reg.subnr;
if (insn->header.access_mode == BRW_ALIGN_1) {
insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset;
insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset;
}
else {
insn->bits2.ia16.src0_subreg_nr = reg.dw1.bits.indirect_offset;
@@ -316,7 +316,7 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
/* FIXME: While this is correct, if the assembler uses that code path
* the opcode generated are different and thus needs a validation
* pass.
if (reg.width == BRW_WIDTH_1 &&
if (reg.width == BRW_WIDTH_1 &&
insn->header.execution_size == BRW_EXECUTE_1) {
insn->bits2.da1.src0_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
insn->bits2.da1.src0_width = BRW_WIDTH_1;
@@ -404,7 +404,7 @@ void brw_set_src1(struct brw_compile *p,
/* FIXME: While this is correct, if the assembler uses that code path
* the opcode generated are different and thus needs a validation
* pass.
if (reg.width == BRW_WIDTH_1 &&
if (reg.width == BRW_WIDTH_1 &&
insn->header.execution_size == BRW_EXECUTE_1) {
insn->bits3.da1.src1_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
insn->bits3.da1.src1_width = BRW_WIDTH_1;
@@ -766,7 +766,7 @@ brw_next_insn(struct brw_compile *p, GLuint opcode)
insn = &p->store[p->nr_insn++];
memcpy(insn, p->current, sizeof(*insn));
/* Reset this one-shot flag:
/* Reset this one-shot flag:
*/
if (p->current->header.destreg__conditionalmod) {
@@ -795,7 +795,7 @@ static struct brw_instruction *brw_alu2(struct brw_compile *p,
struct brw_reg src0,
struct brw_reg src1 )
{
struct brw_instruction *insn = next_insn(p, opcode);
struct brw_instruction *insn = next_insn(p, opcode);
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, src1);
@@ -1084,7 +1084,7 @@ struct brw_instruction *brw_MUL(struct brw_compile *p,
void brw_NOP(struct brw_compile *p)
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src1(p, insn, brw_imm_ud(0x0));
@@ -1098,7 +1098,7 @@ void brw_NOP(struct brw_compile *p)
* Comparisons, if/else/endif
*/
struct brw_instruction *brw_JMPI(struct brw_compile *p,
struct brw_instruction *brw_JMPI(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg src0,
struct brw_reg src1)
@@ -1736,7 +1736,7 @@ void brw_CMP(struct brw_compile *p,
/* Make it so that future instructions will use the computed flag
* value until brw_set_predicate_control_flag_value() is called
* again.
* again.
*/
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
dest.nr == 0) {
@@ -2211,7 +2211,7 @@ void brw_SAMPLE(struct brw_compile *p,
/*printf("%s: zero writemask??\n", __FUNCTION__); */
return;
}
/* Hardware doesn't do destination dependency checking on send
* instructions properly. Add a workaround which generates the
* dependency by other means. In practice it seems like this bug
@@ -2260,11 +2260,11 @@ void brw_SAMPLE(struct brw_compile *p,
brw_MOV(p, retype(m1, BRW_REGISTER_TYPE_UD),
retype(brw_vec8_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_MOV(p, get_element_ud(m1, 2), brw_imm_ud(newmask << 12));
brw_MOV(p, get_element_ud(m1, 2), brw_imm_ud(newmask << 12));
brw_pop_insn_state(p);
src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
dest = offset(dest, dst_offset);
/* For 16-wide dispatch, masked channels are skipped in the
@@ -2278,7 +2278,7 @@ void brw_SAMPLE(struct brw_compile *p,
{
struct brw_instruction *insn;
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
insn = next_insn(p, BRW_OPCODE_SEND);
@@ -2293,7 +2293,7 @@ void brw_SAMPLE(struct brw_compile *p,
binding_table_index,
sampler,
msg_type,
response_length,
response_length,
msg_length,
header_present,
simd_mode,
@@ -2363,9 +2363,9 @@ void brw_urb_WRITE(struct brw_compile *p,
allocate,
used,
msg_length,
response_length,
eot,
writes_complete,
response_length,
eot,
writes_complete,
offset,
swizzle);
}