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https://github.com/tiagovignatti/intel-gpu-tools.git
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Initial gen4asm code.
This commit is contained in:
Eric Anholt
committed by
Damien Lespiau
Damien Lespiau
parent
7ee278f176
commit
22a1063cc0
@@ -0,0 +1,402 @@
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%{
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/*
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* Copyright © 2006 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include <stdio.h>
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#include "gen4asm.h"
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#include "brw_defines.h"
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%}
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%start ROOT
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%union {
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char *s;
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int integer;
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double number;
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struct brw_instruction instruction;
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struct brw_program program;
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struct region {
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int vert_stride, width, horiz_stride;
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} region;
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struct direct_gen_reg {
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int reg_file, reg_nr, subreg_nr;
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} direct_gen_reg;
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double imm32;
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}
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%token SEMICOLON
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%token LPAREN RPAREN
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%token LANGLE RANGLE
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%token LCURLY RCURLY
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%token COMMA
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%token DOT
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%token TYPE_UD, TYPE_D, TYPE_UW, TYPE_W, TYPE_UB, TYPE_B,
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%token TYPE_VF, TYPE_HF, TYPE_V, TYPE_F
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%token ALIGN1
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%token GENREGFILE MSGREGFILE
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%token MOV
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%token MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2
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%token ADD
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%token SEND NULL_TOKEN MATH SAMPLER GATEWAY READ WRITE URB THREAD_SPAWNER
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%token MSGLEN RETURNLEN
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%token <integer> INTEGER
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%token <number> NUMBER
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%type <instruction> instruction unaryinstruction binaryinstruction
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%type <instruction> binaryaccinstruction triinstruction sendinstruction
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%type <instruction> dstoperand dstoperandex dstreg accreg
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%type <instruction> directsrcaccoperand src directsrcoperand srcimm
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%type <instruction> srcacc srcaccimm
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%type <program> instrseq
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%type <integer> unaryop binaryop binaryaccop triop
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%type <integer> regtype srcimmtype execsize dstregion
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%type <integer> gensubregnum msgsubregnum msgtarget
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%type <region> region
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%type <direct_gen_reg> directgenreg directmsgreg
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%type <imm32> imm32
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%%
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ROOT: instrseq
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{
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compiled_program = $1;
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}
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;
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instrseq: instruction SEMICOLON instrseq
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{
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struct brw_program_instruction *list_entry =
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calloc(sizeof(struct brw_program_instruction), 1);
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list_entry->instruction = $1;
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list_entry->next = $3.first;
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$3.first = list_entry;
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$$ = $3;
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}
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| instruction SEMICOLON
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{
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struct brw_program_instruction *list_entry =
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calloc(sizeof(struct brw_program_instruction), 1);
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list_entry->instruction = $1;
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list_entry->next = NULL;
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$$.first = list_entry;
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}
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| error SEMICOLON instrseq
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{
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$$ = $3;
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}
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;
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/* 1.4.1: Instruction groups */
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instruction: unaryinstruction
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| binaryinstruction
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| binaryaccinstruction
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| triinstruction
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;
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unaryinstruction: predicate unaryop execsize dst srcaccimm instoptions
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{
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$$.header.opcode = $2;
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$$.header.execution_size = $3;
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}
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;
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unaryop: MOV { $$ = BRW_OPCODE_MOV; }
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;
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binaryinstruction:
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predicate binaryop execsize dst src srcimm instoptions
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{
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$$.header.opcode = $2;
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$$.header.execution_size = $3;
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}
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;
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binaryop: MUL { $$ = BRW_OPCODE_MUL; }
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binaryaccinstruction:
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predicate binaryaccop execsize dst srcacc srcimm instoptions
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{
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$$.header.opcode = $2;
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$$.header.execution_size = $3;
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}
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;
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binaryaccop: ADD { $$ = BRW_OPCODE_ADD; }
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;
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triinstruction: sendinstruction
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/* XXX formatting of this instruction */
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sendinstruction: predicate SEND INTEGER execsize postdst curdst msgtarget
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MSGLEN INTEGER RETURNLEN INTEGER instoptions
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{
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$$.header.opcode = BRW_OPCODE_SEND;
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$$.header.execution_size = $4;
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$$.header.destreg__conditonalmod = $3;
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}
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/* XXX! */
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postdst: dstoperand
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;
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/* XXX! */
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curdst: directsrcoperand
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;
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msgtarget: NULL_TOKEN { $$ = BRW_MESSAGE_TARGET_NULL; }
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| SAMPLER { $$ = BRW_MESSAGE_TARGET_SAMPLER; }
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| MATH { $$ = BRW_MESSAGE_TARGET_MATH; }
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| GATEWAY { $$ = BRW_MESSAGE_TARGET_GATEWAY; }
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| READ { $$ = BRW_MESSAGE_TARGET_DATAPORT_READ; }
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| WRITE { $$ = BRW_MESSAGE_TARGET_DATAPORT_WRITE; }
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| URB { $$ = BRW_MESSAGE_TARGET_URB; }
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| THREAD_SPAWNER { $$ = BRW_MESSAGE_TARGET_THREAD_SPAWNER; }
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;
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/* 1.4.2: Destination register */
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/** XXX: dstoperandex */
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dst: dstoperand
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/* XXX: dstregion writemask */
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dstoperand: dstreg dstregion regtype
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{
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/* Returns an instruction with just the destination register
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* filled in.
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*/
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$$.bits1 = $1.bits1;
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$$.bits1.da1.dest_reg_type = $2;
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}
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dstoperandex: accreg dstregion regtype
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{
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/* Returns an instruction with just the destination register
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* filled in.
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*/
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$$.bits1 = $1.bits1;
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$$.bits1.da1.dest_reg_type = $2;
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}
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/* XXX: indirectgenreg, directmsgreg, indirectmsgreg */
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dstreg: directgenreg
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{
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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}
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| directmsgreg
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;
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/* 1.4.3: Source register */
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srcaccimm: srcacc
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| imm32 srcimmtype
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{
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$$.bits1.da1.src0_reg_file = BRW_IMMEDIATE_VALUE;
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switch ($2) {
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case BRW_REGISTER_TYPE_UD:
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$$.bits3.ud = $1;
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break;
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case BRW_REGISTER_TYPE_D:
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$$.bits3.id = $1;
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break;
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case BRW_REGISTER_TYPE_F:
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$$.bits3.fd = $1;
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break;
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}
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}
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;
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/* XXX: indirectsrcaccoperand */
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srcacc: directsrcaccoperand
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;
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srcimm: directsrcoperand
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| imm32 srcimmtype
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{
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$$.bits1.da1.src0_reg_file = BRW_IMMEDIATE_VALUE;
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switch ($2) {
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case BRW_REGISTER_TYPE_UD:
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$$.bits3.ud = $1;
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break;
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case BRW_REGISTER_TYPE_D:
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$$.bits3.id = $1;
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break;
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case BRW_REGISTER_TYPE_F:
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$$.bits3.fd = $1;
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break;
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}
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}
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;
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/* XXX: srcaccoperandex, accreg regtype */
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directsrcaccoperand: directsrcoperand
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;
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/* XXX: indirectsrcoperand */
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src: directsrcoperand
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;
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/* XXX: srcmodifier, swizzle srcaccoperandex */
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directsrcoperand: directgenreg region regtype
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{
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/* Returns a source operand in the src0 fields of an
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* instruction.
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*/
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$$.bits1.da1.src0_reg_file = $1.reg_file;
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$$.bits1.da1.src0_reg_type = $3;
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$$.bits2.da1.src0_subreg_nr = $1.subreg_nr;
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$$.bits2.da1.src0_reg_nr = $1.reg_nr;
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$$.bits2.da1.src0_vert_stride = $2.vert_stride;
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$$.bits2.da1.src0_width = $2.width;
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$$.bits2.da1.src0_horiz_stride = $2.horiz_stride;
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}
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;
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/* 1.4.5: Register files and register numbers */
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directgenreg: GENREGFILE INTEGER gensubregnum
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{
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/* Returns an instruction with just the destination register
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* fields filled in.
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*/
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$$.reg_file = BRW_GENERAL_REGISTER_FILE;
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$$.reg_nr = $2;
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$$.subreg_nr = $3;
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}
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gensubregnum: DOT INTEGER
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{
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$$ = $2;
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}
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{
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/* Default to subreg 0 if unspecified. */
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$$ = 0;
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}
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;
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directmsgreg: MSGREGFILE INTEGER msgsubregnum
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{
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/* Returns an instruction with just the destination register
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* fields filled in.
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*/
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$$.reg_file = BRW_GENERAL_REGISTER_FILE;
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$$.reg_nr = $2;
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$$.subreg_nr = $3;
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}
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;
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msgsubregnum: gensubregnum
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;
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/* 1.4.7: Regions */
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dstregion: LANGLE INTEGER RANGLE
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{
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/* Returns a value for a horiz_stride field of an
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* instruction.
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*/
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if ($2 != 1 && $2 != 2 && $2 != 4) {
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fprintf(stderr, "Invalid horiz size %d\n", $2);
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}
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$$ = ffs($2);
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}
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;
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region: LANGLE INTEGER COMMA INTEGER COMMA INTEGER RANGLE
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{
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$$.vert_stride = $2;
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$$.width = $4;
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$$.horiz_stride = $6;
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}
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;
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/* 1.4.8: Types */
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/* regtype returns an integer register type suitable for inserting into an
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* instruction.
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*/
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regtype: TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
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| TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
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| TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
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| TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
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| TYPE_W { $$ = BRW_REGISTER_TYPE_UW; }
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| TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
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| TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
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/* XXX: Add TYPE_VF and TYPE_HF */
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srcimmtype: regtype
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;
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/* 1.4.11: */
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imm32: INTEGER | NUMBER
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/* 1.4.12: Predication and modifiers */
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/* XXX: do the predicate */
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predicate:
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execsize: LPAREN INTEGER RPAREN
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{
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/* Returns a value for the execution_size field of an
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* instruction.
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*/
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if ($2 != 1 && $2 != 2 && $2 != 4 && $2 != 8 && $2 != 16 &&
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$2 != 32) {
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fprintf(stderr, "Invalid execution size %d\n", $2);
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YYERROR;
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}
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$$ = ffs($2);
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}
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;
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/* 1.4.13: Instruction options */
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/* XXX: this is a comma-separated list, really. */
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instoptions: LCURLY instoption RCURLY
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/* XXX: fill me in. alignctrl, comprctrl, threadctrl, depctrl, maskctrl,
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* debugctrl, sendctrl
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*/
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instoption: ALIGN1
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%%
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extern int yylineno;
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void yyerror (char *msg)
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{
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fprintf(stderr, "parse error \"%s\" at line %d, token \"%s\"\n",
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msg, yylineno, lex_text());
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}
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