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https://github.com/tiagovignatti/intel-gpu-tools.git
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71874f4a52
Add generic tools to poke at IOSF sideband. The user needs to manually specify SB port as well as the register. TODO: Maybe add symbolic names for the units? Would avoid having to trawl the docs for the magic hex value. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
86 lines
3.1 KiB
C
86 lines
3.1 KiB
C
/*
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* Copyright © 2009 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifndef INTEL_GPU_TOOLS_H
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#define INTEL_GPU_TOOLS_H
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#include <stdint.h>
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#include <pciaccess.h>
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/* register access helpers from intel_mmio.c */
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extern void *mmio;
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void intel_mmio_use_pci_bar(struct pci_device *pci_dev);
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void intel_mmio_use_dump_file(char *file);
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int intel_register_access_init(struct pci_device *pci_dev, int safe);
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void intel_register_access_fini(void);
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uint32_t intel_register_read(uint32_t reg);
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void intel_register_write(uint32_t reg, uint32_t val);
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int intel_register_access_needs_fakewake(void);
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uint32_t INREG(uint32_t reg);
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void OUTREG(uint32_t reg, uint32_t val);
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/* sideband access functions from intel_iosf.c */
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uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
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void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy);
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uint32_t intel_flisdsi_reg_read(uint32_t reg);
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void intel_flisdsi_reg_write(uint32_t reg, uint32_t val);
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uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg);
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void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val);
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int intel_punit_read(uint8_t addr, uint32_t *val);
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int intel_punit_write(uint8_t addr, uint32_t val);
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int intel_nc_read(uint8_t addr, uint32_t *val);
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int intel_nc_write(uint8_t addr, uint32_t val);
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/* register maps from intel_reg_map.c */
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#ifndef __GTK_DOC_IGNORE__
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#define INTEL_RANGE_RSVD (0<<0) /* Shouldn't be read or written */
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#define INTEL_RANGE_READ (1<<0)
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#define INTEL_RANGE_WRITE (1<<1)
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#define INTEL_RANGE_RW (INTEL_RANGE_READ | INTEL_RANGE_WRITE)
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#define INTEL_RANGE_END (1<<31)
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struct intel_register_range {
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uint32_t base;
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uint32_t size;
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uint32_t flags;
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};
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struct intel_register_map {
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struct intel_register_range *map;
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uint32_t top;
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uint32_t alignment_mask;
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};
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struct intel_register_map intel_get_register_map(uint32_t devid);
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struct intel_register_range *intel_get_register_range(struct intel_register_map map, uint32_t offset, uint32_t mode);
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#endif /* __GTK_DOC_IGNORE__ */
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#endif /* INTEL_GPU_TOOLS_H */
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