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e624fa8a2e
All the cases that simply dump some debug information and couldn't be converted to some of the fancier macros. Some information output removed when it's redundant with the subtest status. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
248 lines
6.8 KiB
C
248 lines
6.8 KiB
C
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Chris Wilson <chris@chris-wilson.co.uk>
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*
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*/
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/*
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* Testcase: Test the relocations through the CPU domain
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*
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* Attempt to stress test performing relocations whilst the batch is in the
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* CPU domain.
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*
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* A freshly allocated buffer starts in the CPU domain, and the pwrite
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* should also be performed whilst in the CPU domain and so we should
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* execute the relocations within the CPU domain. If for any reason one of
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* those steps should land it in the GTT domain, we take the secondary
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* precaution of filling the mappable portion of the GATT.
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*
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* In order to detect whether a relocation fails, we first fill a target
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* buffer with a sequence of invalid commands that would cause the GPU to
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* immediate hang, and then attempt to overwrite them with a legal, if
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* short, batchbuffer using a BLT. Then we come to execute the bo, if the
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* relocation fail and we either copy across all zeros or garbage, then the
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* GPU will hang.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include <drm.h>
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#include "ioctl_wrappers.h"
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#include "drmtest.h"
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#include "intel_bufmgr.h"
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#include "intel_batchbuffer.h"
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#include "intel_io.h"
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#include "intel_chipset.h"
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#include "igt_aux.h"
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static uint32_t use_blt;
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static void copy(int fd, uint32_t batch, uint32_t src, uint32_t dst)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_relocation_entry gem_reloc[2];
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struct drm_i915_gem_exec_object2 gem_exec[3];
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gem_reloc[0].offset = 4 * sizeof(uint32_t);
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gem_reloc[0].delta = 0;
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gem_reloc[0].target_handle = dst;
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gem_reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
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gem_reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
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gem_reloc[0].presumed_offset = 0;
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gem_reloc[1].offset = 7 * sizeof(uint32_t);
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if (intel_gen(intel_get_drm_devid(fd)) >= 8)
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gem_reloc[1].offset += sizeof(uint32_t);
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gem_reloc[1].delta = 0;
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gem_reloc[1].target_handle = src;
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gem_reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
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gem_reloc[1].write_domain = 0;
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gem_reloc[1].presumed_offset = 0;
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memset(gem_exec, 0, sizeof(gem_exec));
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gem_exec[0].handle = src;
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gem_exec[1].handle = dst;
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gem_exec[2].handle = batch;
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gem_exec[2].relocation_count = 2;
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gem_exec[2].relocs_ptr = (uintptr_t)gem_reloc;
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = (uintptr_t)gem_exec;
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execbuf.buffer_count = 3;
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execbuf.batch_len = 4096;
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execbuf.flags = use_blt;
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do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf));
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}
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static void exec(int fd, uint32_t handle)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 gem_exec;
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memset(&gem_exec, 0, sizeof(gem_exec));
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gem_exec.handle = handle;
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = (uintptr_t)&gem_exec;
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execbuf.buffer_count = 1;
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execbuf.batch_len = 4096;
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do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf));
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}
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uint32_t gen6_batch[] = {
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(XY_SRC_COPY_BLT_CMD | 6 |
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XY_SRC_COPY_BLT_WRITE_ALPHA |
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XY_SRC_COPY_BLT_WRITE_RGB),
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(3 << 24 | /* 32 bits */
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0xcc << 16 | /* copy ROP */
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4096),
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0 << 16 | 0, /* dst x1, y1 */
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1 << 16 | 2,
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0, /* dst relocation */
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0 << 16 | 0, /* src x1, y1 */
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4096,
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0, /* src relocation */
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MI_BATCH_BUFFER_END,
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};
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uint32_t gen8_batch[] = {
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(XY_SRC_COPY_BLT_CMD | 8 |
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XY_SRC_COPY_BLT_WRITE_ALPHA |
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XY_SRC_COPY_BLT_WRITE_RGB),
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(3 << 24 | /* 32 bits */
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0xcc << 16 | /* copy ROP */
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4096),
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0 << 16 | 0, /* dst x1, y1 */
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1 << 16 | 2,
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0, /* dst relocation */
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0, /* FIXME */
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0 << 16 | 0, /* src x1, y1 */
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4096,
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0, /* src relocation */
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0, /* FIXME */
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MI_BATCH_BUFFER_END,
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};
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uint32_t *batch = gen6_batch;
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uint32_t batch_size = sizeof(gen6_batch);
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igt_simple_main
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{
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const uint32_t hang[] = {-1, -1, -1, -1};
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const uint32_t end[] = {MI_BATCH_BUFFER_END, 0};
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uint64_t aper_size;
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uint32_t noop;
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uint32_t *handles;
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int fd, i, count;
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fd = drm_open_any();
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noop = intel_get_drm_devid(fd);
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use_blt = 0;
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if (intel_gen(noop) >= 6)
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use_blt = I915_EXEC_BLT;
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if (intel_gen(noop) >= 8) {
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batch = gen8_batch;
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batch_size += 2 * 4;
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}
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aper_size = gem_mappable_aperture_size();
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igt_skip_on_f(intel_get_total_ram_mb() < aper_size / (1024*1024) * 2,
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"not enough mem to run test\n");
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count = aper_size / 4096 * 2;
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if (igt_run_in_simulation())
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count = 10;
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handles = malloc (count * sizeof(uint32_t));
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igt_assert(handles);
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noop = gem_create(fd, 4096);
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gem_write(fd, noop, 0, end, sizeof(end));
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/* fill the entire gart with batches and run them */
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for (i = 0; i < count; i++) {
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uint32_t bad;
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handles[i] = gem_create(fd, 4096);
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gem_write(fd, handles[i], 0, batch, batch_size);
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bad = gem_create(fd, 4096);
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gem_write(fd, bad, 0, hang, sizeof(hang));
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/* launch the newly created batch */
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copy(fd, handles[i], noop, bad);
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exec(fd, bad);
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gem_close(fd, bad);
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igt_progress("gem_cpu_reloc: ", i, 2*count);
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}
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/* And again in reverse to try and catch the relocation code out */
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for (i = 0; i < count; i++) {
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uint32_t bad;
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bad = gem_create(fd, 4096);
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gem_write(fd, bad, 0, hang, sizeof(hang));
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/* launch the newly created batch */
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copy(fd, handles[count-i-1], noop, bad);
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exec(fd, bad);
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gem_close(fd, bad);
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igt_progress("gem_cpu_reloc: ", count+i, 3*count);
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}
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/* Third time lucky? */
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for (i = 0; i < count; i++) {
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uint32_t bad;
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bad = gem_create(fd, 4096);
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gem_write(fd, bad, 0, hang, sizeof(hang));
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/* launch the newly created batch */
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gem_set_domain(fd, handles[i],
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I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
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copy(fd, handles[i], noop, bad);
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exec(fd, bad);
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gem_close(fd, bad);
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igt_progress("gem_cpu_reloc: ", 2*count+i, 3*count);
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}
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igt_info("Test suceeded, cleanup up - this might take a while.\n");
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close(fd);
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}
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