mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
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235 lines
6.2 KiB
C
235 lines
6.2 KiB
C
/**************************************************************************
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*
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* Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#include <inttypes.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include "drm.h"
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#include "drmtest.h"
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#include "intel_batchbuffer.h"
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#include "intel_bufmgr.h"
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#include "intel_chipset.h"
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#include "intel_reg.h"
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#include <i915_drm.h>
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void
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intel_batchbuffer_reset(struct intel_batchbuffer *batch)
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{
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if (batch->bo != NULL) {
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drm_intel_bo_unreference(batch->bo);
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batch->bo = NULL;
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}
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batch->bo = drm_intel_bo_alloc(batch->bufmgr, "batchbuffer",
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BATCH_SZ, 4096);
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batch->ptr = batch->buffer;
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}
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struct intel_batchbuffer *
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intel_batchbuffer_alloc(drm_intel_bufmgr *bufmgr, uint32_t devid)
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{
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struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
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batch->bufmgr = bufmgr;
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batch->devid = devid;
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intel_batchbuffer_reset(batch);
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return batch;
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}
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void
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intel_batchbuffer_free(struct intel_batchbuffer *batch)
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{
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drm_intel_bo_unreference(batch->bo);
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batch->bo = NULL;
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free(batch);
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}
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#define CMD_POLY_STIPPLE_OFFSET 0x7906
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static unsigned int
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flush_on_ring_common(struct intel_batchbuffer *batch, int ring)
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{
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unsigned int used = batch->ptr - batch->buffer;
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if (used == 0)
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return 0;
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if (IS_GEN5(batch->devid)) {
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/* emit gen5 w/a without batch space checks - we reserve that
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* already. */
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*(uint32_t *) (batch->ptr) = CMD_POLY_STIPPLE_OFFSET << 16;
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*(uint32_t *) (batch->ptr) = 0;
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batch->ptr += 8;
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}
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/* Round batchbuffer usage to 2 DWORDs. */
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if ((used & 4) == 0) {
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*(uint32_t *) (batch->ptr) = 0; /* noop */
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batch->ptr += 4;
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}
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/* Mark the end of the buffer. */
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*(uint32_t *)(batch->ptr) = MI_BATCH_BUFFER_END; /* noop */
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batch->ptr += 4;
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return batch->ptr - batch->buffer;
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}
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void
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intel_batchbuffer_flush_on_ring(struct intel_batchbuffer *batch, int ring)
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{
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unsigned int used = flush_on_ring_common(batch, ring);
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if (used == 0)
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return;
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do_or_die(drm_intel_bo_subdata(batch->bo, 0, used, batch->buffer));
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batch->ptr = NULL;
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do_or_die(drm_intel_bo_mrb_exec(batch->bo, used, NULL, 0, 0, ring));
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intel_batchbuffer_reset(batch);
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}
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void
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intel_batchbuffer_flush_with_context(struct intel_batchbuffer *batch,
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drm_intel_context *context)
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{
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int ret;
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unsigned int used = flush_on_ring_common(batch, I915_EXEC_RENDER);
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if (used == 0)
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return;
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ret = drm_intel_bo_subdata(batch->bo, 0, used, batch->buffer);
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assert(ret == 0);
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batch->ptr = NULL;
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ret = drm_intel_gem_bo_context_exec(batch->bo, context, used,
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I915_EXEC_RENDER);
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assert(ret == 0);
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intel_batchbuffer_reset(batch);
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}
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void
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intel_batchbuffer_flush(struct intel_batchbuffer *batch)
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{
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int ring = 0;
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if (HAS_BLT_RING(batch->devid))
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ring = I915_EXEC_BLT;
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intel_batchbuffer_flush_on_ring(batch, ring);
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}
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/* This is the only way buffers get added to the validate list.
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*/
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void
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intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
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drm_intel_bo *buffer, uint32_t delta,
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uint32_t read_domains, uint32_t write_domain,
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int fenced)
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{
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int ret;
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if (batch->ptr - batch->buffer > BATCH_SZ)
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printf("bad relocation ptr %p map %p offset %d size %d\n",
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batch->ptr, batch->buffer,
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(int)(batch->ptr - batch->buffer),
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BATCH_SZ);
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if (fenced)
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ret = drm_intel_bo_emit_reloc_fence(batch->bo, batch->ptr - batch->buffer,
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buffer, delta,
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read_domains, write_domain);
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else
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ret = drm_intel_bo_emit_reloc(batch->bo, batch->ptr - batch->buffer,
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buffer, delta,
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read_domains, write_domain);
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intel_batchbuffer_emit_dword(batch, buffer->offset + delta);
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assert(ret == 0);
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}
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void
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intel_batchbuffer_data(struct intel_batchbuffer *batch,
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const void *data, unsigned int bytes)
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{
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assert((bytes & 3) == 0);
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intel_batchbuffer_require_space(batch, bytes);
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memcpy(batch->ptr, data, bytes);
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batch->ptr += bytes;
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}
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void
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intel_copy_bo(struct intel_batchbuffer *batch,
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drm_intel_bo *dst_bo, drm_intel_bo *src_bo,
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int width, int height)
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{
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uint32_t src_tiling, dst_tiling, swizzle;
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uint32_t src_pitch, dst_pitch;
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uint32_t cmd_bits = 0;
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drm_intel_bo_get_tiling(src_bo, &src_tiling, &swizzle);
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drm_intel_bo_get_tiling(dst_bo, &dst_tiling, &swizzle);
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src_pitch = width * 4;
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if (IS_965(batch->devid) && src_tiling != I915_TILING_NONE) {
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src_pitch /= 4;
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cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
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}
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dst_pitch = width * 4;
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if (IS_965(batch->devid) && dst_tiling != I915_TILING_NONE) {
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dst_pitch /= 4;
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cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
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}
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BEGIN_BATCH(8);
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OUT_BATCH(XY_SRC_COPY_BLT_CMD |
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XY_SRC_COPY_BLT_WRITE_ALPHA |
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XY_SRC_COPY_BLT_WRITE_RGB |
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cmd_bits);
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OUT_BATCH((3 << 24) | /* 32 bits */
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(0xcc << 16) | /* copy ROP */
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dst_pitch);
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OUT_BATCH(0); /* dst x1,y1 */
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OUT_BATCH((height << 16) | width); /* dst x2,y2 */
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OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(0); /* src x1,y1 */
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OUT_BATCH(src_pitch);
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OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
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ADVANCE_BATCH();
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intel_batchbuffer_flush(batch);
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}
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