mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-09 17:06:14 +00:00
98 lines
3.1 KiB
Plaintext
98 lines
3.1 KiB
Plaintext
('DPLLA_CTRL', '0x186014', '')
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('DPLLB_CTRL', '0x186018', '')
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('DPLLAMD_CRTL', '0x18601c', '')
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('DPLLBMD_CRTL', '0x186020', '')
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('RAWCLK_FREQ', '0x186024', '')
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('D_STAT', '0x186104', '')
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('DISPCLK_GATE_D', '0x186200', '')
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('DPPSR_CGDIS', '0x186204', '')
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('RAMCLK_GATE_D', '0x186210', '')
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('CPU_VGACNTRL', '0x001c1000', '')
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('HTOTAL_A', '0x001e0000', '')
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('HBLANK_A', '0x001e0004', '')
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('HSYNC_A', '0x001e0008', '')
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('VTOTAL_A', '0x001e000c', '')
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('VBLANK_A', '0x001e0010', '')
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('VSYNC_A', '0x001e0014', '')
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('PIPEASRC', '0x001e001c', '')
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('VSYNCSHIFT_A', '0x001e0028', '')
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('PIPEA_DATA_M1', '0x001e0030', '')
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('PIPEA_DATA_N1', '0x001e0034', '')
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('PIPEA_DATA_M2', '0x001e0038', '')
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('PIPEA_DATA_N2', '0x001e003c', '')
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('PIPEA_LINK_M1', '0x001e0040', '')
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('PIPEA_LINK_N1', '0x001e0044', '')
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('PIPEA_LINK_M2', '0x001e0048', '')
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('PIPEA_LINK_N2', '0x001e004c', '')
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('HTOTAL_B', '0x001e1000', '')
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('HBLANK_B', '0x001e1004', '')
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('HSYNC_B', '0x001e1008', '')
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('VTOTAL_B', '0x001e100c', '')
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('VBLANK_B', '0x001e1010', '')
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('VSYNC_B', '0x001e1014', '')
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('PIPEBSRC', '0x001e101c', '')
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('VSYNCSHIFT_B', '0x001e1028', '')
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('PIPEB_DATA_M1', '0x001e1030', '')
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('PIPEB_DATA_N1', '0x001e1034', '')
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('PIPEB_DATA_M2', '0x001e1038', '')
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('PIPEB_DATA_N2', '0x001e103c', '')
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('PIPEB_LINK_M1', '0x001e1040', '')
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('PIPEB_LINK_N1', '0x001e1044', '')
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('PIPEB_LINK_M2', '0x001e1048', '')
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('PIPEB_LINK_N2', '0x001e104c', '')
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('ADPA', '0x1e1100', '')
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('PORT_HOTPLUG_EN', '0x1e1110', '')
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('PORT_HOTPLUG_STAT', '0x1e1114', '')
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('SDVO_HDMIB', '0x1e1140', '')
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('SDVO_DP2', '0x1e1154', '')
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('HDMIC', '0x1e1160', '')
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('PORT_HOTPLUG_CTRL', '0x1e1164', '')
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('DP_B', '0x1e4100', '')
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('DP_C', '0x1e4200', '')
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('DPINVGTT', '0x001f002c', '')
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('DSPARB', '0x001f0030', '')
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('FW1', '0x001f0034', '')
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('FW2', '0x001f0038', '')
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('FW3', '0x001f003c', '')
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('FW4', '0x001f0070', '')
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('FW5', '0x001f0074', '')
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('FW6', '0x001f0078', '')
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('FW7', '0x001f007c', '')
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('DDL1', '0x001f0050', '')
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('DDL2', '0x001f0052', '')
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('DSPARB2', '0x001f0060', '')
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('DSPHOWM', '0x001f0064', '')
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('DSPHOWM1', '0x001f0068', '')
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('PIPEACONF', '0x001f0008', '')
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('PIPEASTAT', '0x001f0024', '')
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('DSPACNTR', '0x001f0180', '')
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('DSPABASE', '0x001f0184', '')
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('DSPASTRIDE', '0x001f0188', '')
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('DSPASURF', '0x001f019c', '')
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('DSPATILEOFF', '0x001f01a4', '')
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('PIPEBCONF', '0x001f1008', '')
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('PIPEBSTAT', '0x001f1024', '')
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('DSPBCNTR', '0x001f1180', '')
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('DSPBBASE', '0x001f1184', '')
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('DSPBSTRIDE', '0x001f1188', '')
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('DSPBSURF', '0x001f119c', '')
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('DSPBTILEOFF', '0x001f11a4', '')
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('PIPECCONF', '0x001f2008', '')
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('DSPCCNTR', '0x001f2180', '')
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('DSPCBASE', '0x001f2184', '')
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('DSPCSTRIDE', '0x001f2188', '')
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('DSPCSURF', '0x001f219c', '')
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('DSPCTILEOFF', '0x001f21a4', '')
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('PIPEA_PP_STATUS', '0x001e1200', '')
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('PIPEA_PP_CONTROL', '0x001e1204', '')
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('PIPEA_PP_ON_DELAYS', '0x001e1208', '')
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('PIPEA_PP_OFF_DELAYS', '0x001e120c', '')
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('PIPEA_PP_DIVISOR', '0x001e1210', '')
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('PIPEB_PP_STATUS', '0x001e1300', '')
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('PIPEB_PP_CONTROL', '0x001e1304', '')
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('PIPEB_PP_ON_DELAYS', '0x001e1308', '')
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('PIPEB_PP_OFF_DELAYS', '0x001e130c', '')
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('PIPEB_PP_DIVISOR', '0x001e1310', '')
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('BLC_PWM_CTL2', '0x1e1250', '')
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('BLC_PWM_CTL', '0x1e1254', '')
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