mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-11-04 12:07:12 +00:00
c81d293aed
Apply the new API to all call sites within the test suite using the following semantic patch: // Semantic patch for replacing drm_open_any* with arch-specific drm_open_driver* calls @@ identifier i =~ "\bdrm_open_any\b"; @@ - i() + drm_open_driver(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_master\b"; @@ - i() + drm_open_driver_master(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_render\b"; @@ - i() + drm_open_driver_render(DRIVER_INTEL) @@ identifier i =~ "\b__drm_open_any\b"; @@ - i() + __drm_open_driver(DRIVER_INTEL) Signed-off-by: Micah Fedke <micah.fedke@collabora.co.uk> Signed-off-by: Thomas Wood <thomas.wood@intel.com>
534 lines
16 KiB
C
534 lines
16 KiB
C
/*
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* Copyright © 2010, 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Kenneth Graunke <kenneth@whitecape.org>
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*
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* While documentation for performance counters is suspiciously missing from the
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* Sandybridge PRM, they were documented in Volume 1 Part 3 of the Ironlake PRM.
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*
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* A lot of the Ironlake PRM actually unintentionally documents Sandybridge
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* due to mistakes made when updating the documentation for Gen6+. Many of
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* these mislabeled sections carried forward to the public documentation.
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*
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* The Ironlake PRMs have been publicly available since 2010 and are online at:
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* https://01.org/linuxgraphics/documentation/2010-intel-core-processor-family
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*/
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#include <unistd.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <err.h>
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#include <sys/ioctl.h>
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#include "drm.h"
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#include "i915_drm.h"
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#include "drmtest.h"
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#include "intel_io.h"
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#include "intel_bufmgr.h"
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#include "intel_batchbuffer.h"
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#include "intel_chipset.h"
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#define GEN5_COUNTER_COUNT 29
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const char *gen5_counter_names[GEN5_COUNTER_COUNT] = {
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"cycles the CS unit is starved",
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"cycles the CS unit is stalled",
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"cycles the VF unit is starved",
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"cycles the VF unit is stalled",
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"cycles the VS unit is starved",
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"cycles the VS unit is stalled",
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"cycles the GS unit is starved",
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"cycles the GS unit is stalled",
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"cycles the CL unit is starved",
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"cycles the CL unit is stalled",
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"cycles the SF unit is starved",
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"cycles the SF unit is stalled",
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"cycles the WZ unit is starved",
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"cycles the WZ unit is stalled",
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"Z buffer read/write ",
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"cycles each EU was active ",
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"cycles each EU was suspended ",
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"cycles threads loaded all EUs",
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"cycles filtering active ",
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"cycles PS threads executed ",
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"subspans written to RC ",
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"bytes read for texture reads ",
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"texels returned from sampler ",
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"polygons not culled ",
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"clocks MASF has valid message",
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"64b writes/reads from RC ",
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"reads on dataport ",
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"clocks MASF has valid msg not consumed by sampler",
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"cycles any EU is stalled for math",
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};
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#define GEN6_COUNTER_COUNT 29
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/**
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* Sandybridge: Counter Select = 001
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* A0 A1 A2 A3 A4 TIMESTAMP RPT_ID
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* A5 A6 A7 A8 A9 A10 A11 A12
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* A13 A14 A15 A16 A17 A18 A19 A20
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* A21 A22 A23 A24 A25 A26 A27 A28
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*/
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const int gen6_counter_format = 1;
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/**
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* Names for aggregating counters A0-A28.
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*
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* While the Ironlake PRM clearly documents that there are 29 counters (A0-A28),
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* it only lists the names for 28 of them; one is missing. However, careful
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* examination reveals a pattern: there are five GS counters (Active, Stall,
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* Core Stall, # threads loaded, and ready but not running time). There are
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* also five PS counters, in the same order. But there are only four VS
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* counters listed - the number of VS threads loaded is missing. Presumably,
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* it exists and is counter 5, and the rest are shifted over one place.
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*/
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const char *gen6_counter_names[GEN6_COUNTER_COUNT] = {
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[0] = "Aggregated Core Array Active",
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[1] = "Aggregated Core Array Stalled",
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[2] = "Vertex Shader Active Time",
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[3] = "Vertex Shader Stall Time",
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[4] = "Vertex Shader Stall Time - Core Stall",
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[5] = "# VS threads loaded",
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[6] = "Vertex Shader Ready but not running time",
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[7] = "Geometry Shader Active Time",
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[8] = "Geometry Shader Stall Time",
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[9] = "Geometry Shader Stall Time - Core Stall",
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[10] = "# GS threads loaded",
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[11] = "Geometry Shader ready but not running Time",
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[12] = "Pixel Shader Active Time",
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[13] = "Pixel Shader Stall Time",
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[14] = "Pixel Shader Stall Time - Core Stall",
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[15] = "# PS threads loaded",
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[16] = "Pixel Shader ready but not running Time",
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[17] = "Early Z Test Pixels Passing",
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[18] = "Early Z Test Pixels Failing",
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[19] = "Early Stencil Test Pixels Passing",
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[20] = "Early Stencil Test Pixels Failing",
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[21] = "Pixel Kill Count",
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[22] = "Alpha Test Pixels Failed",
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[23] = "Post PS Stencil Pixels Failed",
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[24] = "Post PS Z buffer Pixels Failed",
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[25] = "Pixels/samples Written in the frame buffer",
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[26] = "GPU Busy",
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[27] = "CL active and not stalled",
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[28] = "SF active and stalled",
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};
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#define GEN7_COUNTER_COUNT 44
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/**
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* Names for aggregating counters A0-A44. Uninitialized fields are "Reserved."
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*/
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const char *gen7_counter_names[GEN7_COUNTER_COUNT] = {
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/* A0:
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* The sum of all cycles on all cores actively executing instructions
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* This does not count the time taken to service Send instructions.
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* This time is considered by shader active counters to give the result.
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*/
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[0] = "Aggregated Core Array Active",
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/* A1:
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* The sum of all cycles on all cores where the EU is not idle and is
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* not actively executing ISA instructions. Generally this means that
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* all loaded threads on the EU are stalled on some data dependency,
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* but this also includes the time during which the TS is loading the
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* thread dispatch header into the EU prior to thread execution and no
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* other thread is fully loaded.
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*/
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[1] = "Aggregated Core Array Stalled",
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/* A2:
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* Total time in clocks the vertex shader spent active on all cores.
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*/
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[2] = "Vertex Shader Active Time",
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/* A4:
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* Total time in clocks the vertex shader spent stalled on all cores -
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* and the entire core was stalled as well.
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*/
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[4] = "Vertex Shader Stall Time - Core Stall",
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/* A5: Number of VS threads loaded at any given time in the EUs. */
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[5] = "# VS threads loaded",
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/* A7:
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* Total time in clocks the Hull shader spent active on all cores.
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*/
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[7] = "Hull Shader Active Time",
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/* A9:
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* Total time in clocks the Hull shader spent stalled on all cores -
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* and the entire core was stalled as well.
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*/
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[9] = "Hull Shader Stall Time - Core Stall",
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/* A10: Number of HS threads loaded at any given time in the EUs. */
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[10] = "# HS threads loaded",
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/* A12:
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* Total time in clocks the Domain shader spent active on all cores.
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*/
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[12] = "Domain Shader Active Time",
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/* A14:
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* Total time in clocks the domain shader spent stalled on all cores -
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* and the entire core was stalled as well.
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*/
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[14] = "Domain Shader Stall Time - Core Stall",
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/* A15: Number of DS threads loaded at any given time in the EUs. */
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[15] = "# DS threads loaded",
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/* A17:
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* Total time in clocks the compute shader spent active on all cores.
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*/
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[17] = "Compute Shader Active Time",
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/* A19:
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* Total time in clocks the compute shader spent stalled on all cores -
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* and the entire core was stalled as well.
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*/
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[19] = "Compute Shader Stall Time - Core Stall",
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/* A20: Number of CS threads loaded at any given time in the EUs. */
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[20] = "# CS threads loaded",
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/* A22:
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* Total time in clocks the geometry shader spent active on all cores.
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*/
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[22] = "Geometry Shader Active Time",
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/* A24:
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* Total time in clocks the geometry shader spent stalled on all cores -
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* and the entire core was stalled as well.
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*/
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[24] = "Geometry Shader Stall Time - Core Stall",
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/* A25: Number of GS threads loaded at any time in the EUs. */
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[25] = "# GS threads loaded",
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/* A27:
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* Total time in clocks the pixel shader spent active on all cores.
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*/
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[27] = "Pixel Shader Active Time",
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/* A29:
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* Total time in clocks the pixel shader spent stalled on all cores -
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* and the entire core was stalled as well.
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*/
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[29] = "Pixel Shader Stall Time - Core Stall",
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/* A30: Number of PS threads loaded at any given time in the EUs. */
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[30] = "# PS threads loaded",
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/* A32: Count of pixels that pass the fast check (8x8). */
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[32] = "HiZ Fast Z Test Pixels Passing",
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/* A33: Count of pixels that fail the fast check (8x8). */
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[33] = "HiZ Fast Z Test Pixels Failing",
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/* A34: Count of pixels passing the slow check (2x2). */
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[34] = "Slow Z Test Pixels Passing",
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/* A35: Count of pixels that fail the slow check (2x2). */
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[35] = "Slow Z Test Pixels Failing",
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/* A36: Number of pixels/samples killed in the pixel shader.
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* Ivybridge/Baytrail Erratum: Count reported is 2X the actual count for
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* dual source render target messages i.e. when PS has two output colors.
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*/
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[36] = "Pixel Kill Count",
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/* A37:
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* Number of pixels/samples that fail alpha-test. Alpha to coverage
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* may have some challenges in per-pixel invocation.
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*/
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[37] = "Alpha Test Pixels Failed",
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/* A38:
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* Number of pixels/samples failing stencil test after the pixel shader
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* has executed.
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*/
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[38] = "Post PS Stencil Pixels Failed",
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/* A39:
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* Number of pixels/samples fail Z test after the pixel shader has
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* executed.
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*/
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[39] = "Post PS Z buffer Pixels Failed",
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/* A40:
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* Number of render target writes. MRT scenarios will cause this
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* counter to increment multiple times.
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*/
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[40] = "3D/GPGPU Render Target Writes",
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/* A41: Render engine is not idle.
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*
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* GPU Busy aggregate counter doesn't increment under the following
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* conditions:
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*
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* 1. Context Switch in Progress.
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* 2. GPU stalled on executing MI_WAIT_FOR_EVENT.
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* 3. GPU stalled on execution MI_SEMAPHORE_MBOX.
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* 4. RCS idle but other parts of GPU active (e.g. only media engines
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* active)
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*/
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[41] = "Render Engine Busy",
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/* A42:
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* VSunit is stalling VF (upstream unit) and starving HS (downstream
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* unit).
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*/
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[42] = "VS bottleneck",
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/* A43:
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* GSunit is stalling DS (upstream unit) and starving SOL (downstream
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* unit).
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*/
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[43] = "GS bottleneck",
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};
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/**
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* Ivybridge - Counter Select = 101
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* A4 A3 A2 A1 A0 TIMESTAMP ReportID
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* A12 A11 A10 A9 A8 A7 A6 A5
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* A20 A19 A18 A17 A16 A15 A14 A13
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* A28 A27 A26 A25 A24 A23 A22 A21
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* A36 A35 A34 A33 A32 A31 A30 A29
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* A44 A43 A42 A41 A40 A39 A38 A37
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* C3 C2 C1 C0 B3 B2 B1 B0
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* C11 C10 C9 C8 C7 C6 C5 C4
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*/
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const int gen7_counter_format = 5; /* 0b101 */
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int have_totals = 0;
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uint32_t *totals;
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uint32_t *last_counter;
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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/* DW0 */
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#define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))
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#define MI_COUNTER_SET_0 (0 << 6)
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#define MI_COUNTER_SET_1 (1 << 6)
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/* DW1 */
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#define MI_COUNTER_ADDRESS_GTT (1 << 0)
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/* DW2: report ID */
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/**
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* According to the Sandybridge PRM, Volume 1, Part 1, page 48,
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* MI_REPORT_PERF_COUNT is now opcode 0x28. The Ironlake PRM, Volume 1,
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* Part 3 details how it works.
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*/
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/* DW0 */
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#define GEN6_MI_REPORT_PERF_COUNT (0x28 << 23)
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/* DW1 and 2 are the same as above */
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/* OACONTROL exists on Gen6+ but is documented in the Ironlake PRM */
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#define OACONTROL 0x2360
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# define OACONTROL_COUNTER_SELECT_SHIFT 2
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# define PERFORMANCE_COUNTER_ENABLE (1 << 0)
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static void
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gen5_get_counters(void)
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{
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int i;
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drm_intel_bo *stats_bo;
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uint32_t *stats_result;
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stats_bo = drm_intel_bo_alloc(bufmgr, "stats", 4096, 4096);
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BEGIN_BATCH(6, 2);
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OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_0);
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OUT_RELOC(stats_bo,
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I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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0);
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OUT_BATCH(0);
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OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | MI_COUNTER_SET_1);
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OUT_RELOC(stats_bo,
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I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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64);
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OUT_BATCH(0);
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ADVANCE_BATCH();
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intel_batchbuffer_flush(batch);
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drm_intel_bo_map(stats_bo, 0);
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stats_result = stats_bo->virtual;
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/* skip REPORT_ID, TIMESTAMP */
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stats_result += 3;
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for (i = 0 ; i < GEN5_COUNTER_COUNT; i++) {
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totals[i] += stats_result[i] - last_counter[i];
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last_counter[i] = stats_result[i];
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}
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drm_intel_bo_unmap(stats_bo);
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drm_intel_bo_unreference(stats_bo);
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}
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static void
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gen6_get_counters(void)
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{
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int i;
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drm_intel_bo *stats_bo;
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uint32_t *stats_result;
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/* Map from counter names to their index in the buffer object */
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static const int buffer_index[GEN6_COUNTER_COUNT] =
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{
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7, 6, 5, 4, 3,
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15, 14, 13, 12, 11, 10, 9, 8,
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23, 22, 21, 20, 19, 18, 17, 16,
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31, 30, 29, 28, 27, 26, 25, 24,
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};
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stats_bo = drm_intel_bo_alloc(bufmgr, "stats", 4096, 4096);
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BEGIN_BATCH(3, 1);
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OUT_BATCH(GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
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OUT_RELOC(stats_bo,
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I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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MI_COUNTER_ADDRESS_GTT);
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OUT_BATCH(0);
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ADVANCE_BATCH();
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intel_batchbuffer_flush_on_ring(batch, I915_EXEC_RENDER);
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drm_intel_bo_map(stats_bo, 0);
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stats_result = stats_bo->virtual;
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for (i = 0; i < GEN6_COUNTER_COUNT; i++) {
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totals[i] += stats_result[buffer_index[i]] - last_counter[i];
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last_counter[i] = stats_result[buffer_index[i]];
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}
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drm_intel_bo_unmap(stats_bo);
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drm_intel_bo_unreference(stats_bo);
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}
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static void
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gen7_get_counters(void)
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{
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int i;
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drm_intel_bo *stats_bo;
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uint32_t *stats_result;
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stats_bo = drm_intel_bo_alloc(bufmgr, "stats", 4096, 4096);
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BEGIN_BATCH(3, 1);
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OUT_BATCH(GEN6_MI_REPORT_PERF_COUNT | (3 - 2));
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OUT_RELOC(stats_bo,
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I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
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OUT_BATCH(0);
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ADVANCE_BATCH();
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intel_batchbuffer_flush_on_ring(batch, I915_EXEC_RENDER);
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drm_intel_bo_map(stats_bo, 0);
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stats_result = stats_bo->virtual;
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/* skip REPORT_ID, TIMESTAMP */
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stats_result += 3;
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for (i = 0; i < GEN7_COUNTER_COUNT; i++) {
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/* Ignore "Reserved" counters */
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if (!gen7_counter_names[i])
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continue;
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totals[i] += stats_result[i] - last_counter[i];
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last_counter[i] = stats_result[i];
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}
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drm_intel_bo_unmap(stats_bo);
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drm_intel_bo_unreference(stats_bo);
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}
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#define STATS_CHECK_FREQUENCY 100
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#define STATS_REPORT_FREQUENCY 2
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int
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main(int argc, char **argv)
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{
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uint32_t devid;
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int counter_format;
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int counter_count;
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const char **counter_name;
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void (*get_counters)(void);
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int i;
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char clear_screen[] = {0x1b, '[', 'H',
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0x1b, '[', 'J',
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0x0};
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bool oacontrol = true;
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int fd;
|
|
int l;
|
|
|
|
fd = drm_open_driver(DRIVER_INTEL);
|
|
devid = intel_get_drm_devid(fd);
|
|
|
|
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
|
|
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
|
|
batch = intel_batchbuffer_alloc(bufmgr, devid);
|
|
|
|
if (IS_GEN5(devid)) {
|
|
counter_name = gen5_counter_names;
|
|
counter_count = GEN5_COUNTER_COUNT;
|
|
get_counters = gen5_get_counters;
|
|
oacontrol = false;
|
|
} else if (IS_GEN6(devid)) {
|
|
counter_name = gen6_counter_names;
|
|
counter_count = GEN6_COUNTER_COUNT;
|
|
counter_format = gen6_counter_format;
|
|
get_counters = gen6_get_counters;
|
|
} else if (IS_GEN7(devid)) {
|
|
counter_name = gen7_counter_names;
|
|
counter_count = GEN7_COUNTER_COUNT;
|
|
counter_format = gen7_counter_format;
|
|
get_counters = gen7_get_counters;
|
|
} else {
|
|
printf("This tool is not yet supported on your platform.\n");
|
|
abort();
|
|
}
|
|
|
|
if (oacontrol) {
|
|
/* Forcewake */
|
|
intel_register_access_init(intel_get_pci_device(), 0);
|
|
|
|
/* Enable performance counters */
|
|
intel_register_write(OACONTROL,
|
|
counter_format << OACONTROL_COUNTER_SELECT_SHIFT |
|
|
PERFORMANCE_COUNTER_ENABLE);
|
|
}
|
|
|
|
totals = calloc(counter_count, sizeof(uint32_t));
|
|
last_counter = calloc(counter_count, sizeof(uint32_t));
|
|
|
|
for (;;) {
|
|
for (l = 0; l < STATS_CHECK_FREQUENCY; l++) {
|
|
printf("%s", clear_screen);
|
|
|
|
if (l % (STATS_CHECK_FREQUENCY / STATS_REPORT_FREQUENCY) == 0) {
|
|
if (have_totals) {
|
|
for (i = 0; i < counter_count; i++) {
|
|
/* Ignore "Reserved" counters */
|
|
if (!counter_name[i])
|
|
continue;
|
|
printf("%s: %u\n", counter_name[i],
|
|
totals[i]);
|
|
totals[i] = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
get_counters();
|
|
have_totals = 1;
|
|
|
|
usleep(1000000 / STATS_CHECK_FREQUENCY);
|
|
}
|
|
}
|
|
|
|
if (oacontrol) {
|
|
/* Disable performance counters */
|
|
intel_register_write(OACONTROL, 0);
|
|
|
|
/* Forcewake */
|
|
intel_register_access_fini();
|
|
}
|
|
|
|
free(totals);
|
|
free(last_counter);
|
|
|
|
return 0;
|
|
}
|