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https://github.com/tiagovignatti/intel-gpu-tools.git
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f4dfa37e85
This provides a macro that allows us to update all the arbitrary blit commands we have stuck throughout the code. It assumes we don't actually use 64b relocs (which is currently true). This also allows us to easily find all the areas we need to update later when we really use the upper dword. This block was done mostly with a sed job, and represents the easier in test blit implementations. v2 by Oscar: s/OUT_BATCH/BEGIN_BATCH in BLIT_COPY_BATCH_START CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
139 lines
4.0 KiB
C
139 lines
4.0 KiB
C
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Daniel Vetter <daniel.vetter@ffwll.ch>
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include "drm.h"
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#include "i915_drm.h"
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#include "drmtest.h"
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#include "intel_bufmgr.h"
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#include "intel_batchbuffer.h"
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#include "intel_gpu_tools.h"
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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/* Testcase: check whether the libdrm vma limiter works
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*
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* We've had reports of the X server exhausting the default rlimit of 64k vma's
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* in the kernel. libdrm has grown facilities to limit the vma caching since,
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* this checks whether they actually work.
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*
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* This one checks whether mmaps of unused cached bos are also properly reaped.
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*/
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/* we do both cpu and gtt maps, so only need half of 64k to exhaust */
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int main(int argc, char **argv)
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{
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int fd;
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int i;
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char *ptr;
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drm_intel_bo *load_bo;
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igt_skip_on_simulation();
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fd = drm_open_any();
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
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load_bo = drm_intel_bo_alloc(bufmgr, "target bo", 1024*4096, 4096);
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igt_assert(load_bo);
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drm_intel_bufmgr_gem_set_vma_cache_size(bufmgr, 500);
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/* IMPORTANT: we need to enable buffer reuse, otherwise we won't test
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* the libdrm bo cache! */
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drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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/* put some load onto the gpu to keep the light buffers active for long
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* enough */
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for (i = 0; i < 10000; i++) {
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BLIT_COPY_BATCH_START(batch->devid, 0);
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OUT_BATCH((3 << 24) | /* 32 bits */
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(0xcc << 16) | /* copy ROP */
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4096);
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OUT_BATCH(0); /* dst x1,y1 */
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OUT_BATCH((1024 << 16) | 512);
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OUT_RELOC(load_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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BLIT_RELOC_UDW(batch->devid);
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OUT_BATCH((0 << 16) | 512); /* src x1, y1 */
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OUT_BATCH(4096);
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OUT_RELOC(load_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
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BLIT_RELOC_UDW(batch->devid);
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ADVANCE_BATCH();
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}
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#define GROUP_SZ 100
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for (i = 0; i < 68000; ) {
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int j;
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drm_intel_bo *bo[GROUP_SZ];
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for (j = 0; j < GROUP_SZ; j++, i++) {
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bo[j] = drm_intel_bo_alloc(bufmgr, "mmap bo", 4096, 4096);
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igt_assert(bo[j]);
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drm_intel_gem_bo_map_gtt(bo[j]);
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ptr = bo[j]->virtual;
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igt_assert(ptr);
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*ptr = 'c';
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drm_intel_gem_bo_unmap_gtt(bo[j]);
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/* put it onto the active list ... */
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BEGIN_BATCH(6);
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OUT_BATCH(XY_COLOR_BLT_CMD |
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XY_COLOR_BLT_WRITE_ALPHA |
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XY_COLOR_BLT_WRITE_RGB);
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OUT_BATCH((3 << 24) | /* 32 bits */
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128);
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OUT_BATCH(0); /* dst x1,y1 */
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OUT_BATCH((1 << 16) | 1);
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OUT_RELOC(bo[j], I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(0xffffffff); /* color */
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ADVANCE_BATCH();
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}
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intel_batchbuffer_flush(batch);
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for (j = 0; j < GROUP_SZ; j++)
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drm_intel_bo_unreference(bo[j]);
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}
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intel_batchbuffer_free(batch);
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drm_intel_bufmgr_destroy(bufmgr);
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close(fd);
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return 0;
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}
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