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4fc76adf31
In Valleyview the DPLL and lane control registers are accessible only through side band fabric called DPIO. Added two tools to read and write registers residing in this space. v2: Moved the core read/write functions to lib/intel_dpio.c based on Ben's feedback Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
95 lines
3.0 KiB
C
95 lines
3.0 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Vijay Purushothaman <vijay.a.purushothaman@intel.com>
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*
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*/
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <err.h>
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#include "intel_gpu_tools.h"
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static uint32_t intel_display_reg_read(uint32_t reg)
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{
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struct pci_device *dev = intel_get_pci_device();
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if (IS_VALLEYVIEW(dev->device_id))
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reg += VLV_DISPLAY_BASE;
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return (*(volatile uint32_t*)((volatile char*)mmio + reg));
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}
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static void intel_display_reg_write(uint32_t reg, uint32_t val)
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{
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volatile uint32_t *ptr;
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struct pci_device *dev = intel_get_pci_device();
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if (IS_VALLEYVIEW(dev->device_id))
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reg += VLV_DISPLAY_BASE;
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ptr = (volatile uint32_t*)((volatile char*)mmio + reg);
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*ptr = val;
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}
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/*
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* In SoCs like Valleyview some of the PLL & Lane control registers
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* can be accessed only through IO side band fabric called DPIO
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*/
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uint32_t
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intel_dpio_reg_read(uint32_t reg)
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{
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/* Check whether the side band fabric is ready to accept commands */
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do {
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usleep(1);
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} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
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intel_display_reg_write(DPIO_REG, reg);
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intel_display_reg_write(DPIO_PKT, DPIO_RID |
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DPIO_OP_READ | DPIO_PORTID | DPIO_BYTE);
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do {
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usleep(1);
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} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
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return intel_display_reg_read(DPIO_DATA);
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}
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/*
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* In SoCs like Valleyview some of the PLL & Lane control registers
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* can be accessed only through IO side band fabric called DPIO
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*/
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void
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intel_dpio_reg_write(uint32_t reg, uint32_t val)
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{
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/* Check whether the side band fabric is ready to accept commands */
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do {
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usleep(1);
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} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
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intel_display_reg_write(DPIO_DATA, val);
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intel_display_reg_write(DPIO_REG, reg);
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intel_display_reg_write(DPIO_PKT, DPIO_RID |
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DPIO_OP_WRITE | DPIO_PORTID | DPIO_BYTE);
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do {
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usleep(1);
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} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
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}
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