mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
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95e89f0ede
As usual de-inline functions for gtkdoc to see them. I've decided to exclude the register map stuff since that's not terribly interesting. Aside: gtkdoc falls over when the title of a section contains a slash, hence why it reads "IO" instead of "I/O". The fun ... Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
148 lines
3.5 KiB
C
148 lines
3.5 KiB
C
#include <unistd.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <err.h>
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#include <errno.h>
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#include "intel_io.h"
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#include "intel_reg.h"
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#define TIMEOUT_US 500000
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static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
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uint32_t *val)
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{
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int timeout = 0;
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uint32_t cmd, devfn, be, bar;
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int is_read = (opcode == PUNIT_OPCODE_REG_READ ||
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opcode == DPIO_OPCODE_REG_READ);
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bar = 0;
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be = 0xf;
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devfn = 16;
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cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
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(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
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(bar << IOSF_BAR_SHIFT);
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if (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
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fprintf(stderr, "warning: pcode (%s) mailbox access failed\n",
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is_read ? "read" : "write");
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return -EAGAIN;
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}
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intel_register_write(VLV_IOSF_ADDR, addr);
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if (!is_read)
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intel_register_write(VLV_IOSF_DATA, *val);
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intel_register_write(VLV_IOSF_DOORBELL_REQ, cmd);
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do {
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usleep(1);
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timeout++;
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} while (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY &&
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timeout < TIMEOUT_US);
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if (timeout >= TIMEOUT_US) {
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fprintf(stderr, "timeout waiting for pcode %s (%d) to finish\n",
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is_read ? "read" : "write", addr);
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return -ETIMEDOUT;
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}
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if (is_read)
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*val = intel_register_read(VLV_IOSF_DATA);
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intel_register_write(VLV_IOSF_DATA, 0);
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return 0;
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}
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/**
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* intel_punit_read:
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* @addr: register offset
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* @val: pointer to starge for the read result
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*
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* 32-bit read of the register at @offset through the P-Unit sideband port.
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*
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* Returns:
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* 0 when the register access succeeded, negative errno code on failure.
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*/
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int intel_punit_read(uint8_t addr, uint32_t *val)
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{
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return vlv_sideband_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ, addr, val);
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}
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/**
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* intel_punit_write:
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* @addr: register offset
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* @val: value to write
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*
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* 32-bit write of the register at @offset through the P-Unit sideband port.
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*
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* Returns:
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* 0 when the register access succeeded, negative errno code on failure.
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*/
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int intel_punit_write(uint8_t addr, uint32_t val)
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{
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return vlv_sideband_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE, addr, &val);
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}
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/**
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* intel_nc_read:
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* @addr: register offset
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* @val: pointer to starge for the read result
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*
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* 32-bit read of the register at @offset through the NC sideband port.
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*
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* Returns:
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* 0 when the register access succeeded, negative errno code on failure.
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*/
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int intel_nc_read(uint8_t addr, uint32_t *val)
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{
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return vlv_sideband_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_READ, addr, val);
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}
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/**
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* intel_nc_write:
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* @addr: register offset
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* @val: value to write
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*
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* 32-bit write of the register at @offset through the NC sideband port.
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*
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* Returns:
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* 0 when the register access succeeded, negative errno code on failure.
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*/
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int intel_nc_write(uint8_t addr, uint32_t val)
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{
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return vlv_sideband_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_WRITE, addr, &val);
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}
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/**
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* intel_dpio_reg_read:
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* @reg: register offset
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* @phy: DPIO PHY to use
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*
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* 32-bit read of the register at @offset through the DPIO sideband port.
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*
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* Returns:
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* The value read from the register.
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*/
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uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
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{
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uint32_t val;
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vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_READ, reg, &val);
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return val;
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}
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/**
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* intel_dpio_reg_write:
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* @reg: register offset
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* @val: value to write
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* @phy: dpio PHY to use
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*
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* 32-bit write of the register at @offset through the DPIO sideband port.
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*/
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void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
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{
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vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_WRITE, reg, &val);
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}
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