ntel-gpu-tools

mirror of https://github.com/tiagovignatti/intel-gpu-tools.git synced 2025-06-08 16:36:14 +00:00

History

Zhao Yakui 88e5f1fdf8 assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8

Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
  >add.sat (16) r[a0.5,0]<1>:uw     r[a0.5,0]<16;16,1>:uw  0x0080:uw
  >add.sat (16) r[a0.5,32]<1>:uw    r[a0.5,32]<16;16,1>:uw 0x0080:uw

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

2013-11-06 09:39:41 -08:00

doc

Add autotools build system, and rearrange directory layout.

2013-03-04 15:54:23 +00:00

test

assembler: Disable the declare test

2013-08-20 18:25:52 +01:00

.gitignore

Update .gitignore a bit

2013-11-04 19:49:10 +01:00

brw_compat.h

assembler/bdw: Add gen8_instruction from mesa

2013-11-06 09:34:35 -08:00

brw_context.c

assembler: Introduce struct brw_context

2013-03-04 15:54:37 +00:00

brw_context.h

assembler: Put struct opcode_desc back in brw_context.h

2013-03-04 15:54:41 +00:00

brw_defines.h

assembler: Add support for D and UD in 3-src instructions

2013-03-04 15:54:41 +00:00

brw_disasm.c

assembler: Mark format() as PRINTFLIKE in the disassembler

2013-03-04 15:54:42 +00:00

brw_eu_compact.c

assembler: Import brw_eu_compact.c

2013-03-04 15:54:37 +00:00

brw_eu_debug.c

assembler: Remove trailing white space

2013-03-04 15:54:42 +00:00

brw_eu_emit.c

assembler: Don't use GL types

2013-03-04 15:54:42 +00:00

brw_eu_util.c

assembler: Don't use GL types

2013-03-04 15:54:42 +00:00

brw_eu.c

assembler: Don't use GL types

2013-03-04 15:54:42 +00:00

brw_eu.h

assembler: Don't use GL types

2013-03-04 15:54:42 +00:00

brw_reg.h

assembler: Update the disassembler code

2013-03-04 15:54:37 +00:00

brw_structs.h

assembler: Don't use GL types

2013-03-04 15:54:42 +00:00

disasm-main.c

assembler/bdw: Add the start of a gen8 disassembler

2013-11-06 09:39:28 -08:00

gen4asm.h

assembler/bdw: Support some basic gen8 intructions

2013-11-06 09:34:35 -08:00

gen8_disasm.c

assembler/bdw: Add the start of a gen8 disassembler

2013-11-06 09:39:28 -08:00

gen8_instruction.c

assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8

2013-11-06 09:39:41 -08:00

gen8_instruction.h

assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8

2013-11-06 09:39:41 -08:00

gram.y

assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8

2013-11-06 09:39:41 -08:00

intel-gen4asm.pc.in

add intel-gen4asm.pc.in

2013-03-04 15:54:26 +00:00

lex.l

assembler: Add support for the SENDC instruction.

2013-05-22 13:58:36 -07:00

main.c

assembler/bdw: Set jip/uip offsets used by flow control instructions

2013-11-06 09:39:41 -08:00

Makefile.am

assembler/bdw: Add the start of a gen8 disassembler

2013-11-06 09:39:28 -08:00

ralloc.c

assembler: Import ralloc from Mesa

2013-03-04 15:54:37 +00:00

ralloc.h

assembler: Import ralloc from Mesa

2013-03-04 15:54:37 +00:00

README

More renaming of gen4asm -> intel-gen4asm, plus README update.

2013-03-04 15:54:25 +00:00

TODO

Update the TODO with more tasks and a bit more description.

2013-03-04 15:54:25 +00:00

README

intel-gen4asm is a program to compile an assembly language for the Intel 965
Express Chipset.  It has been used to construct programs for textured video in
the 2d driver.

Some examples of gen4 assembly programs are in the doc/examples directory.

Note that the language parsed by this assembler is not exactly what the final
language is going to look like.  In particular, the send instructions need to
be cleaned up and made more reasonable to program with.