mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-11-04 12:07:12 +00:00
248 lines
7.8 KiB
C
248 lines
7.8 KiB
C
#include <stdlib.h>
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#include <sys/ioctl.h>
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include "drm.h"
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#include "i915_drm.h"
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#include "drmtest.h"
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#include "intel_bufmgr.h"
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#include "intel_batchbuffer.h"
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#include "intel_io.h"
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#include "i830_reg.h"
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#include "rendercopy.h"
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#define TB0C_LAST_STAGE (1 << 31)
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#define TB0C_RESULT_SCALE_1X (0 << 29)
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#define TB0C_RESULT_SCALE_2X (1 << 29)
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#define TB0C_RESULT_SCALE_4X (2 << 29)
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#define TB0C_OP_ARG1 (1 << 25)
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#define TB0C_OP_MODULE (3 << 25)
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#define TB0C_OUTPUT_WRITE_CURRENT (0 << 24)
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#define TB0C_OUTPUT_WRITE_ACCUM (1 << 24)
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#define TB0C_ARG3_REPLICATE_ALPHA (1<<23)
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#define TB0C_ARG3_INVERT (1<<22)
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#define TB0C_ARG3_SEL_XXX
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#define TB0C_ARG2_REPLICATE_ALPHA (1<<17)
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#define TB0C_ARG2_INVERT (1<<16)
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#define TB0C_ARG2_SEL_ONE (0 << 12)
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#define TB0C_ARG2_SEL_FACTOR (1 << 12)
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#define TB0C_ARG2_SEL_TEXEL0 (6 << 12)
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#define TB0C_ARG2_SEL_TEXEL1 (7 << 12)
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#define TB0C_ARG2_SEL_TEXEL2 (8 << 12)
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#define TB0C_ARG2_SEL_TEXEL3 (9 << 12)
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#define TB0C_ARG1_REPLICATE_ALPHA (1<<11)
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#define TB0C_ARG1_INVERT (1<<10)
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#define TB0C_ARG1_SEL_ONE (0 << 6)
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#define TB0C_ARG1_SEL_TEXEL0 (6 << 6)
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#define TB0C_ARG1_SEL_TEXEL1 (7 << 6)
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#define TB0C_ARG1_SEL_TEXEL2 (8 << 6)
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#define TB0C_ARG1_SEL_TEXEL3 (9 << 6)
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#define TB0C_ARG0_REPLICATE_ALPHA (1<<5)
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#define TB0C_ARG0_SEL_XXX
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#define TB0A_CTR_STAGE_ENABLE (1<<31)
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#define TB0A_RESULT_SCALE_1X (0 << 29)
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#define TB0A_RESULT_SCALE_2X (1 << 29)
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#define TB0A_RESULT_SCALE_4X (2 << 29)
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#define TB0A_OP_ARG1 (1 << 25)
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#define TB0A_OP_MODULE (3 << 25)
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#define TB0A_OUTPUT_WRITE_CURRENT (0<<24)
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#define TB0A_OUTPUT_WRITE_ACCUM (1<<24)
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#define TB0A_CTR_STAGE_SEL_BITS_XXX
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#define TB0A_ARG3_SEL_XXX
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#define TB0A_ARG3_INVERT (1<<17)
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#define TB0A_ARG2_INVERT (1<<16)
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#define TB0A_ARG2_SEL_ONE (0 << 12)
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#define TB0A_ARG2_SEL_TEXEL0 (6 << 12)
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#define TB0A_ARG2_SEL_TEXEL1 (7 << 12)
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#define TB0A_ARG2_SEL_TEXEL2 (8 << 12)
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#define TB0A_ARG2_SEL_TEXEL3 (9 << 12)
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#define TB0A_ARG1_INVERT (1<<10)
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#define TB0A_ARG1_SEL_ONE (0 << 6)
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#define TB0A_ARG1_SEL_TEXEL0 (6 << 6)
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#define TB0A_ARG1_SEL_TEXEL1 (7 << 6)
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#define TB0A_ARG1_SEL_TEXEL2 (8 << 6)
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#define TB0A_ARG1_SEL_TEXEL3 (9 << 6)
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static void gen2_emit_invariant(struct intel_batchbuffer *batch)
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{
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int i;
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for (i = 0; i < 4; i++) {
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OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(i));
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OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | MAP_UNIT(i) |
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DISABLE_TEX_STREAM_BUMP |
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ENABLE_TEX_STREAM_COORD_SET | TEX_STREAM_COORD_SET(i) |
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ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(i));
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OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
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OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(i));
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}
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OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
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OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
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TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
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TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
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TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
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OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
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OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
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OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
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OUT_BATCH(_3DSTATE_W_STATE_CMD);
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OUT_BATCH(MAGIC_W_STATE_DWORD1);
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OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
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OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
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DISABLE_INDPT_ALPHA_BLEND |
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ENABLE_ALPHA_BLENDFUNC | ABLENDFUNC_ADD);
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OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
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OUT_BATCH(0);
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OUT_BATCH(_3DSTATE_MODES_1_CMD |
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ENABLE_COLR_BLND_FUNC | BLENDFUNC_ADD |
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ENABLE_SRC_BLND_FACTOR | SRC_BLND_FACT(BLENDFACTOR_ONE) |
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ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
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OUT_BATCH(_3DSTATE_ENABLES_1_CMD |
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DISABLE_LOGIC_OP |
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DISABLE_STENCIL_TEST |
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DISABLE_DEPTH_BIAS |
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DISABLE_SPEC_ADD |
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DISABLE_FOG |
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DISABLE_ALPHA_TEST |
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DISABLE_DEPTH_TEST |
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ENABLE_COLOR_BLEND);
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OUT_BATCH(_3DSTATE_ENABLES_2_CMD |
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DISABLE_STENCIL_WRITE |
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DISABLE_DITHER |
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DISABLE_DEPTH_WRITE |
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ENABLE_COLOR_MASK |
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ENABLE_COLOR_WRITE |
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ENABLE_TEX_CACHE);
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}
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static void gen2_emit_target(struct intel_batchbuffer *batch,
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struct igt_buf *dst)
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{
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uint32_t tiling;
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tiling = 0;
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if (dst->tiling != I915_TILING_NONE)
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tiling = BUF_3D_TILED_SURFACE;
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if (dst->tiling == I915_TILING_Y)
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tiling |= BUF_3D_TILE_WALK_Y;
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OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
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OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->stride));
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OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
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OUT_BATCH(COLR_BUF_ARGB8888 |
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DSTORG_HORT_BIAS(0x8) |
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DSTORG_VERT_BIAS(0x8));
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OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
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OUT_BATCH(0);
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OUT_BATCH(0); /* ymin, xmin */
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OUT_BATCH(DRAW_YMAX(igt_buf_height(dst) - 1) |
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DRAW_XMAX(igt_buf_width(dst) - 1));
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OUT_BATCH(0); /* yorig, xorig */
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}
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static void gen2_emit_texture(struct intel_batchbuffer *batch,
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struct igt_buf *src,
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int unit)
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{
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uint32_t tiling;
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tiling = 0;
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if (src->tiling != I915_TILING_NONE)
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tiling = TM0S1_TILED_SURFACE;
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if (src->tiling == I915_TILING_Y)
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tiling |= TM0S1_TILE_WALK;
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OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 | LOAD_TEXTURE_MAP(unit) | 4);
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OUT_RELOC(src->bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
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OUT_BATCH((igt_buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT |
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(igt_buf_width(src) - 1) << TM0S1_WIDTH_SHIFT |
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MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling);
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OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
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OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT |
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FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |
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MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT);
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OUT_BATCH(0); /* default color */
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OUT_BATCH(_3DSTATE_MAP_COORD_SET_CMD | TEXCOORD_SET(unit) |
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ENABLE_TEXCOORD_PARAMS | TEXCOORDS_ARE_NORMAL |
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TEXCOORDTYPE_CARTESIAN |
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ENABLE_ADDR_V_CNTL | TEXCOORD_ADDR_V_MODE(TEXCOORDMODE_CLAMP_BORDER) |
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ENABLE_ADDR_U_CNTL | TEXCOORD_ADDR_U_MODE(TEXCOORDMODE_CLAMP_BORDER));
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}
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static void gen2_emit_copy_pipeline(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
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OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
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DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
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DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
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DISABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
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OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
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LOAD_TEXTURE_BLEND_STAGE(0) | 1);
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OUT_BATCH(TB0C_LAST_STAGE | TB0C_RESULT_SCALE_1X |
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TB0C_OUTPUT_WRITE_CURRENT |
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TB0C_OP_ARG1 | TB0C_ARG1_SEL_TEXEL0);
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OUT_BATCH(TB0A_RESULT_SCALE_1X | TB0A_OUTPUT_WRITE_CURRENT |
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TB0A_OP_ARG1 | TB0A_ARG1_SEL_TEXEL0);
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}
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void gen2_render_copyfunc(struct intel_batchbuffer *batch,
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drm_intel_context *context,
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struct igt_buf *src, unsigned src_x, unsigned src_y,
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unsigned width, unsigned height,
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struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
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{
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gen2_emit_invariant(batch);
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gen2_emit_copy_pipeline(batch);
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gen2_emit_target(batch, dst);
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gen2_emit_texture(batch, src, 0);
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OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
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I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
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OUT_BATCH(1<<12);
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OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
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OUT_BATCH(S8_ENABLE_COLOR_BUFFER_WRITE);
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OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD | TEXCOORDFMT_2D << 0);
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OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (3*4 -1));
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emit_vertex(batch, dst_x + width);
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emit_vertex(batch, dst_y + height);
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emit_vertex_normalized(batch, src_x + width, igt_buf_width(src));
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emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
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emit_vertex(batch, dst_x);
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emit_vertex(batch, dst_y + height);
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emit_vertex_normalized(batch, src_x, igt_buf_width(src));
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emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
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emit_vertex(batch, dst_x);
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emit_vertex(batch, dst_y);
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emit_vertex_normalized(batch, src_x, igt_buf_width(src));
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emit_vertex_normalized(batch, src_y, igt_buf_height(src));
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intel_batchbuffer_flush(batch);
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}
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