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https://github.com/tiagovignatti/intel-gpu-tools.git
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804e11f40d
Add a header that includes all the headers for the library. This allows reorganisation of the library without affecting programs using it and also simplifies the headers that need to be included to use the library. Signed-off-by: Thomas Wood <thomas.wood@intel.com>
108 lines
2.7 KiB
C
108 lines
2.7 KiB
C
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
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*
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*/
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#include "igt.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include "drm.h"
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#include "intel_bufmgr.h"
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#include "i830_reg.h"
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IGT_TEST_DESCRIPTION("Basic check of non-secure batches.");
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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/*
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* Testcase: Basic check of non-secure batches
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*
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* This test tries to stop the render ring with a MI_LOAD_REG command, which
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* should fail if the non-secure handling works correctly.
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*/
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static int num_rings = 1;
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static void
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mi_lri_loop(void)
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{
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int i;
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srandom(0xdeadbeef);
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for (i = 0; i < 0x100; i++) {
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int ring = random() % num_rings + 1;
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BEGIN_BATCH(4, 0);
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OUT_BATCH(MI_LOAD_REGISTER_IMM);
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OUT_BATCH(0x203c); /* RENDER RING CTL */
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OUT_BATCH(0); /* try to stop the ring */
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OUT_BATCH(MI_NOOP);
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ADVANCE_BATCH();
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intel_batchbuffer_flush_on_ring(batch, ring);
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}
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}
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igt_simple_main
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{
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int fd;
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int devid;
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fd = drm_open_any();
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devid = intel_get_drm_devid(fd);
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if (HAS_BSD_RING(devid))
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num_rings++;
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if (HAS_BLT_RING(devid))
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num_rings++;
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igt_info("num rings detected: %i\n", num_rings);
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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igt_assert(bufmgr);
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drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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batch = intel_batchbuffer_alloc(bufmgr, devid);
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igt_assert(batch);
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mi_lri_loop();
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gem_quiescent_gpu(fd);
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intel_batchbuffer_free(batch);
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drm_intel_bufmgr_destroy(bufmgr);
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close(fd);
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}
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