mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-08 16:36:14 +00:00
725da6ee74
rendercopy does the batch buffer flush internally, so if we want to use it with multiple contexts, we need to pass the context in from caller. v2: Modify rendercopy_gen8 as well Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
571 lines
15 KiB
C
571 lines
15 KiB
C
#include "rendercopy.h"
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#include "gen7_render.h"
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#include <assert.h>
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#define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
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static const uint32_t ps_kernel[][4] = {
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{ 0x0080005a, 0x2e2077bd, 0x000000c0, 0x008d0040 },
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{ 0x0080005a, 0x2e6077bd, 0x000000d0, 0x008d0040 },
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{ 0x02800031, 0x21801fa9, 0x008d0e20, 0x08840001 },
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{ 0x00800001, 0x2e2003bd, 0x008d0180, 0x00000000 },
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{ 0x00800001, 0x2e6003bd, 0x008d01c0, 0x00000000 },
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{ 0x00800001, 0x2ea003bd, 0x008d0200, 0x00000000 },
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{ 0x00800001, 0x2ee003bd, 0x008d0240, 0x00000000 },
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{ 0x05800031, 0x20001fa8, 0x008d0e20, 0x90031000 },
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};
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static uint32_t
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batch_used(struct intel_batchbuffer *batch)
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{
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return batch->state - batch->buffer;
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}
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static uint32_t
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batch_align(struct intel_batchbuffer *batch, uint32_t align)
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{
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uint32_t offset = batch_used(batch);
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offset = ALIGN(offset, align);
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batch->state = batch->buffer + offset;
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return offset;
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}
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static void *
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batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
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{
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uint32_t offset = batch_align(batch, align);
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batch->state += size;
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return memset(batch->buffer + offset, 0, size);
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}
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static uint32_t
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batch_offset(struct intel_batchbuffer *batch, void *ptr)
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{
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return (uint8_t *)ptr - batch->buffer;
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}
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static uint32_t
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batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
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{
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return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
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}
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static void
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gen7_render_flush(struct intel_batchbuffer *batch,
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drm_intel_context *context, uint32_t batch_end)
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{
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int ret;
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ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
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if (ret == 0)
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ret = drm_intel_gem_bo_context_exec(batch->bo, context,
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batch_end, 0);
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assert(ret == 0);
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}
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static uint32_t
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gen7_tiling_bits(uint32_t tiling)
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{
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switch (tiling) {
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default: assert(0);
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case I915_TILING_NONE: return 0;
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case I915_TILING_X: return GEN7_SURFACE_TILED;
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case I915_TILING_Y: return GEN7_SURFACE_TILED | GEN7_SURFACE_TILED_Y;
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}
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}
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static uint32_t
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gen7_bind_buf(struct intel_batchbuffer *batch,
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struct scratch_buf *buf,
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uint32_t format,
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int is_dst)
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{
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uint32_t *ss;
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uint32_t write_domain, read_domain;
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int ret;
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if (is_dst) {
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write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
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} else {
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write_domain = 0;
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read_domain = I915_GEM_DOMAIN_SAMPLER;
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}
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ss = batch_alloc(batch, sizeof(*ss), 32);
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ss[0] = (GEN7_SURFACE_2D << GEN7_SURFACE_TYPE_SHIFT |
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gen7_tiling_bits(buf->tiling) |
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format << GEN7_SURFACE_FORMAT_SHIFT);
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ss[1] = buf->bo->offset;
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ss[2] = ((buf_width(buf) - 1) << GEN7_SURFACE_WIDTH_SHIFT |
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(buf_height(buf) - 1) << GEN7_SURFACE_HEIGHT_SHIFT);
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ss[3] = (buf->stride - 1) << GEN7_SURFACE_PITCH_SHIFT;
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ss[4] = 0;
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ss[5] = 0;
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ss[6] = 0;
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ss[7] = 0;
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if (IS_HASWELL(batch->devid))
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ss[7] |= HSW_SURFACE_SWIZZLE(RED, GREEN, BLUE, ALPHA);
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ret = drm_intel_bo_emit_reloc(batch->bo,
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batch_offset(batch, ss) + 4,
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buf->bo, 0,
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read_domain, write_domain);
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assert(ret == 0);
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return batch_offset(batch, ss);
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}
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static void
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gen7_emit_vertex_elements(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_VERTEX_ELEMENTS |
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((2 * (1 + 2)) + 1 - 2));
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OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
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GEN7_SURFACEFORMAT_R32G32B32A32_FLOAT << GEN7_VE0_FORMAT_SHIFT |
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0 << GEN7_VE0_OFFSET_SHIFT);
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OUT_BATCH(GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_0_SHIFT |
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GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_1_SHIFT |
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GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
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GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_3_SHIFT);
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/* x,y */
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OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
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GEN7_SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT |
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0 << GEN7_VE0_OFFSET_SHIFT); /* offsets vb in bytes */
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OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT |
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GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT |
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GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
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GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT);
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/* s,t */
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OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
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GEN7_SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT |
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4 << GEN7_VE0_OFFSET_SHIFT); /* offset vb in bytes */
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OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT |
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GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT |
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GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
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GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT);
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}
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static uint32_t
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gen7_create_vertex_buffer(struct intel_batchbuffer *batch,
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uint32_t src_x, uint32_t src_y,
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uint32_t dst_x, uint32_t dst_y,
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uint32_t width, uint32_t height)
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{
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uint16_t *v;
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v = batch_alloc(batch, 12*sizeof(*v), 8);
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v[0] = dst_x + width;
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v[1] = dst_y + height;
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v[2] = src_x + width;
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v[3] = src_y + height;
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v[4] = dst_x;
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v[5] = dst_y + height;
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v[6] = src_x;
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v[7] = src_y + height;
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v[8] = dst_x;
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v[9] = dst_y;
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v[10] = src_x;
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v[11] = src_y;
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return batch_offset(batch, v);
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}
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static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch,
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int src_x, int src_y,
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int dst_x, int dst_y,
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int width, int height)
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{
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uint32_t offset;
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offset = gen7_create_vertex_buffer(batch,
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src_x, src_y,
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dst_x, dst_y,
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width, height);
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OUT_BATCH(GEN7_3DSTATE_VERTEX_BUFFERS | (5 - 2));
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OUT_BATCH(0 << GEN7_VB0_BUFFER_INDEX_SHIFT |
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GEN7_VB0_VERTEXDATA |
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GEN7_VB0_ADDRESS_MODIFY_ENABLE |
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4*2 << GEN7_VB0_BUFFER_PITCH_SHIFT);
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset);
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OUT_BATCH(~0);
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OUT_BATCH(0);
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}
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static uint32_t
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gen7_bind_surfaces(struct intel_batchbuffer *batch,
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struct scratch_buf *src,
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struct scratch_buf *dst)
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{
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uint32_t *binding_table;
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binding_table = batch_alloc(batch, 8, 32);
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binding_table[0] =
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gen7_bind_buf(batch, dst, GEN7_SURFACEFORMAT_B8G8R8A8_UNORM, 1);
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binding_table[1] =
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gen7_bind_buf(batch, src, GEN7_SURFACEFORMAT_B8G8R8A8_UNORM, 0);
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return batch_offset(batch, binding_table);
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}
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static void
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gen7_emit_binding_table(struct intel_batchbuffer *batch,
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struct scratch_buf *src,
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struct scratch_buf *dst)
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{
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OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
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OUT_BATCH(gen7_bind_surfaces(batch, src, dst));
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}
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static void
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gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct scratch_buf *dst)
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{
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OUT_BATCH(GEN7_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
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OUT_BATCH(0);
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OUT_BATCH((buf_height(dst) - 1) << 16 | (buf_width(dst) - 1));
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OUT_BATCH(0);
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}
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static uint32_t
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gen7_create_blend_state(struct intel_batchbuffer *batch)
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{
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struct gen7_blend_state *blend;
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blend = batch_alloc(batch, sizeof(*blend), 64);
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blend->blend0.dest_blend_factor = GEN7_BLENDFACTOR_ZERO;
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blend->blend0.source_blend_factor = GEN7_BLENDFACTOR_ONE;
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blend->blend0.blend_func = GEN7_BLENDFUNCTION_ADD;
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blend->blend1.post_blend_clamp_enable = 1;
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blend->blend1.pre_blend_clamp_enable = 1;
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return batch_offset(batch, blend);
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}
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static void
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gen7_emit_state_base_address(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2));
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OUT_BATCH(0);
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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}
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static uint32_t
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gen7_create_cc_viewport(struct intel_batchbuffer *batch)
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{
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struct gen7_cc_viewport *vp;
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vp = batch_alloc(batch, sizeof(*vp), 32);
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vp->min_depth = -1.e35;
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vp->max_depth = 1.e35;
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return batch_offset(batch, vp);
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}
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static void
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gen7_emit_cc(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
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OUT_BATCH(gen7_create_blend_state(batch));
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OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
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OUT_BATCH(gen7_create_cc_viewport(batch));
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}
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static uint32_t
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gen7_create_sampler(struct intel_batchbuffer *batch)
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{
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struct gen7_sampler_state *ss;
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ss = batch_alloc(batch, sizeof(*ss), 32);
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ss->ss0.min_filter = GEN7_MAPFILTER_NEAREST;
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ss->ss0.mag_filter = GEN7_MAPFILTER_NEAREST;
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ss->ss3.r_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
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ss->ss3.s_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
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ss->ss3.t_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
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ss->ss3.non_normalized_coord = 1;
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return batch_offset(batch, ss);
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}
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static void
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gen7_emit_sampler(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
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OUT_BATCH(gen7_create_sampler(batch));
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}
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static void
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gen7_emit_multisample(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE | (4 - 2));
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OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
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GEN7_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN7_3DSTATE_SAMPLE_MASK | (2 - 2));
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OUT_BATCH(1);
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}
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static void
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gen7_emit_urb(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
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OUT_BATCH(8); /* in 1KBs */
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/* num of VS entries must be divisible by 8 if size < 9 */
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OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
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OUT_BATCH((64 << GEN7_URB_ENTRY_NUMBER_SHIFT) |
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(2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
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(1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
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OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
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OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
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OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
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OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
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OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
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OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
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}
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static void
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gen7_emit_vs(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_VS | (6 - 2));
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OUT_BATCH(0); /* no VS kernel */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* pass-through */
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}
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static void
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gen7_emit_hs(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
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OUT_BATCH(0); /* no HS kernel */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* pass-through */
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}
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static void
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gen7_emit_te(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen7_emit_ds(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen7_emit_gs(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_GS | (7 - 2));
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OUT_BATCH(0); /* no GS kernel */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* pass-through */
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}
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static void
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gen7_emit_streamout(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen7_emit_sf(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_SF | (7 - 2));
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OUT_BATCH(0);
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OUT_BATCH(GEN7_3DSTATE_SF_CULL_NONE);
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OUT_BATCH(2 << GEN7_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen7_emit_sbe(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
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OUT_BATCH(1 << GEN7_SBE_NUM_OUTPUTS_SHIFT |
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1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
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1 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
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OUT_BATCH(0);
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OUT_BATCH(0); /* dw4 */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* dw8 */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* dw12 */
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OUT_BATCH(0);
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OUT_BATCH(0);
|
|
}
|
|
|
|
static void
|
|
gen7_emit_ps(struct intel_batchbuffer *batch)
|
|
{
|
|
int threads;
|
|
|
|
if (IS_HASWELL(batch->devid))
|
|
threads = 40 << HSW_PS_MAX_THREADS_SHIFT | 1 << HSW_PS_SAMPLE_MASK_SHIFT;
|
|
else
|
|
threads = 40 << IVB_PS_MAX_THREADS_SHIFT;
|
|
|
|
OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2));
|
|
OUT_BATCH(batch_copy(batch, ps_kernel, sizeof(ps_kernel), 64));
|
|
OUT_BATCH(1 << GEN7_PS_SAMPLER_COUNT_SHIFT |
|
|
2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
|
|
OUT_BATCH(0); /* scratch address */
|
|
OUT_BATCH(threads |
|
|
GEN7_PS_16_DISPATCH_ENABLE |
|
|
GEN7_PS_ATTRIBUTE_ENABLE);
|
|
OUT_BATCH(6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
}
|
|
|
|
static void
|
|
gen7_emit_clip(struct intel_batchbuffer *batch)
|
|
{
|
|
OUT_BATCH(GEN7_3DSTATE_CLIP | (4 - 2));
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0); /* pass-through */
|
|
OUT_BATCH(0);
|
|
|
|
OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
|
|
OUT_BATCH(0);
|
|
}
|
|
|
|
static void
|
|
gen7_emit_wm(struct intel_batchbuffer *batch)
|
|
{
|
|
OUT_BATCH(GEN7_3DSTATE_WM | (3 - 2));
|
|
OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
|
|
GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
|
|
OUT_BATCH(0);
|
|
}
|
|
|
|
static void
|
|
gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
|
|
{
|
|
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
|
|
OUT_BATCH(GEN7_SURFACE_NULL << GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
|
|
GEN7_DEPTHFORMAT_D32_FLOAT << GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
|
|
OUT_BATCH(0); /* disable depth, stencil and hiz */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
|
|
OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
}
|
|
|
|
#define BATCH_STATE_SPLIT 2048
|
|
void gen7_render_copyfunc(struct intel_batchbuffer *batch,
|
|
drm_intel_context *context,
|
|
struct scratch_buf *src, unsigned src_x, unsigned src_y,
|
|
unsigned width, unsigned height,
|
|
struct scratch_buf *dst, unsigned dst_x, unsigned dst_y)
|
|
{
|
|
uint32_t batch_end;
|
|
|
|
intel_batchbuffer_flush_with_context(batch, context);
|
|
|
|
batch->state = &batch->buffer[BATCH_STATE_SPLIT];
|
|
|
|
OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_3D);
|
|
|
|
gen7_emit_state_base_address(batch);
|
|
gen7_emit_multisample(batch);
|
|
gen7_emit_urb(batch);
|
|
gen7_emit_vs(batch);
|
|
gen7_emit_hs(batch);
|
|
gen7_emit_te(batch);
|
|
gen7_emit_ds(batch);
|
|
gen7_emit_gs(batch);
|
|
gen7_emit_clip(batch);
|
|
gen7_emit_sf(batch);
|
|
gen7_emit_wm(batch);
|
|
gen7_emit_streamout(batch);
|
|
gen7_emit_null_depth_buffer(batch);
|
|
|
|
gen7_emit_cc(batch);
|
|
gen7_emit_sampler(batch);
|
|
gen7_emit_sbe(batch);
|
|
gen7_emit_ps(batch);
|
|
gen7_emit_vertex_elements(batch);
|
|
gen7_emit_vertex_buffer(batch,
|
|
src_x, src_y, dst_x, dst_y, width, height);
|
|
gen7_emit_binding_table(batch, src, dst);
|
|
gen7_emit_drawing_rectangle(batch, dst);
|
|
|
|
OUT_BATCH(GEN7_3DPRIMITIVE | (7- 2));
|
|
OUT_BATCH(GEN7_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
|
|
OUT_BATCH(3);
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(1); /* single instance */
|
|
OUT_BATCH(0); /* start instance location */
|
|
OUT_BATCH(0); /* index buffer offset, ignored */
|
|
|
|
OUT_BATCH(MI_BATCH_BUFFER_END);
|
|
|
|
batch_end = batch->ptr - batch->buffer;
|
|
batch_end = ALIGN(batch_end, 8);
|
|
assert(batch_end < BATCH_STATE_SPLIT);
|
|
|
|
gen7_render_flush(batch, context, batch_end);
|
|
intel_batchbuffer_reset(batch);
|
|
}
|