mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-11-04 03:58:27 +00:00
66e0bf66da
It's all about good looking APIs. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
941 lines
19 KiB
C
941 lines
19 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <stdio.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include "igt_stats.h"
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#define U64_MAX ((uint64_t)~0ULL)
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#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
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#define WARN(cond, msg) printf(msg)
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#define KHz(x) (1000 * (x))
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#define MHz(x) KHz(1000 * (x))
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#define abs_diff(a, b) ({ \
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typeof(a) __a = (a); \
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typeof(b) __b = (b); \
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(void) (&__a == &__b); \
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__a > __b ? (__a - __b) : (__b - __a); })
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static inline uint64_t div64_u64(uint64_t dividend, uint64_t divisor)
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{
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return dividend / divisor;
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}
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static inline uint64_t div_u64(uint64_t dividend, uint32_t divisor)
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{
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return dividend / divisor;
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}
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struct skl_wrpll_params {
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uint32_t dco_fraction;
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uint32_t dco_integer;
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uint32_t qdiv_ratio;
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uint32_t qdiv_mode;
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uint32_t kdiv;
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uint32_t pdiv;
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uint32_t central_freq;
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/* for this test code only */
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uint64_t central_freq_hz;
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unsigned int p0, p1, p2;
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};
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static bool
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skl_ddi_calculate_wrpll1(int clock /* in Hz */,
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struct skl_wrpll_params *wrpll_params)
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{
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uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
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uint64_t dco_central_freq[3] = {8400000000ULL,
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9000000000ULL,
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9600000000ULL};
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uint32_t min_dco_pdeviation = 100; /* DCO freq must be within +1%/-6% */
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uint32_t min_dco_ndeviation = 600; /* of the DCO central freq */
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uint32_t min_dco_index = 3;
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uint32_t P0[4] = {1, 2, 3, 7};
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uint32_t P2[4] = {1, 2, 3, 5};
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bool found = false;
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uint32_t candidate_p = 0;
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uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
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uint32_t candidate_p2[3] = {0};
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uint32_t dco_central_freq_deviation[3];
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uint32_t i, P1, k, dco_count;
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bool retry_with_odd = false;
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/* Determine P0, P1 or P2 */
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for (dco_count = 0; dco_count < 3; dco_count++) {
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found = false;
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candidate_p =
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div64_u64(dco_central_freq[dco_count], afe_clock);
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if (retry_with_odd == false)
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candidate_p = (candidate_p % 2 == 0 ?
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candidate_p : candidate_p + 1);
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for (P1 = 1; P1 < candidate_p; P1++) {
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for (i = 0; i < 4; i++) {
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if (!(P0[i] != 1 || P1 == 1))
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continue;
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for (k = 0; k < 4; k++) {
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if (P1 != 1 && P2[k] != 2)
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continue;
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if (candidate_p == P0[i] * P1 * P2[k]) {
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/* Found possible P0, P1, P2 */
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found = true;
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candidate_p0[dco_count] = P0[i];
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candidate_p1[dco_count] = P1;
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candidate_p2[dco_count] = P2[k];
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goto found;
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}
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}
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}
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}
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found:
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if (found) {
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uint64_t dco_freq = candidate_p * afe_clock;
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#if 0
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printf("Trying with (%d,%d,%d)\n",
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candidate_p0[dco_count],
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candidate_p1[dco_count],
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candidate_p2[dco_count]);
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#endif
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dco_central_freq_deviation[dco_count] =
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div64_u64(10000 *
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abs_diff(dco_freq,
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dco_central_freq[dco_count]),
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dco_central_freq[dco_count]);
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#if 0
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printf("Deviation %d\n",
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dco_central_freq_deviation[dco_count]);
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printf("dco_freq: %"PRIu64", "
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"dco_central_freq %"PRIu64"\n",
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dco_freq, dco_central_freq[dco_count]);
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#endif
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/* positive deviation */
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if (dco_freq > dco_central_freq[dco_count]) {
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if (dco_central_freq_deviation[dco_count] <
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min_dco_pdeviation) {
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min_dco_pdeviation =
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dco_central_freq_deviation[dco_count];
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min_dco_index = dco_count;
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}
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/* negative deviation */
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} else if (dco_central_freq_deviation[dco_count] <
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min_dco_ndeviation) {
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min_dco_ndeviation =
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dco_central_freq_deviation[dco_count];
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min_dco_index = dco_count;
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}
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}
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if (min_dco_index > 2 && dco_count == 2) {
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/* oh well, we tried... */
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if (retry_with_odd)
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break;
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retry_with_odd = true;
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dco_count = 0;
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}
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}
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if (min_dco_index > 2) {
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WARN(1, "No valid values found for the given pixel clock\n");
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return false;
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} else {
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uint64_t dco_freq;
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wrpll_params->central_freq = dco_central_freq[min_dco_index];
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switch (dco_central_freq[min_dco_index]) {
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case 9600000000ULL:
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wrpll_params->central_freq = 0;
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break;
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case 9000000000ULL:
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wrpll_params->central_freq = 1;
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break;
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case 8400000000ULL:
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wrpll_params->central_freq = 3;
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}
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switch (candidate_p0[min_dco_index]) {
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case 1:
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wrpll_params->pdiv = 0;
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break;
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case 2:
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wrpll_params->pdiv = 1;
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break;
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case 3:
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wrpll_params->pdiv = 2;
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break;
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case 7:
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wrpll_params->pdiv = 4;
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break;
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default:
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WARN(1, "Incorrect PDiv\n");
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}
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switch (candidate_p2[min_dco_index]) {
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case 5:
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wrpll_params->kdiv = 0;
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break;
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case 2:
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wrpll_params->kdiv = 1;
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break;
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case 3:
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wrpll_params->kdiv = 2;
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break;
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case 1:
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wrpll_params->kdiv = 3;
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break;
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default:
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WARN(1, "Incorrect KDiv\n");
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}
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wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
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wrpll_params->qdiv_mode =
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(wrpll_params->qdiv_ratio == 1) ? 0 : 1;
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dco_freq = candidate_p0[min_dco_index] *
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candidate_p1[min_dco_index] *
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candidate_p2[min_dco_index] * afe_clock;
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/*
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* Intermediate values are in Hz.
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* Divide by MHz to match bsepc
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*/
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wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
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wrpll_params->dco_fraction =
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div_u64(((div_u64(dco_freq, 24) -
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wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
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}
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/* for this unit test only */
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wrpll_params->central_freq_hz = dco_central_freq[min_dco_index];
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wrpll_params->p0 = candidate_p0[min_dco_index];
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wrpll_params->p1 = candidate_p1[min_dco_index];
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wrpll_params->p2 = candidate_p2[min_dco_index];
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return true;
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}
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struct skl_wrpll_context {
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uint64_t min_deviation; /* current minimal deviation */
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uint64_t central_freq; /* chosen central freq */
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uint64_t dco_freq; /* chosen dco freq */
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unsigned int p; /* chosen divider */
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};
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static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
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{
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memset(ctx, 0, sizeof(*ctx));
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ctx->min_deviation = U64_MAX;
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}
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/* DCO freq must be within +1%/-6% of the DCO central freq */
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#define SKL_MAX_PDEVIATION 100
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#define SKL_MAX_NDEVIATION 600
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/*
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* Returns true if we're sure to have found the definitive divider (ie
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* deviation == 0).
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*/
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static bool skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
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uint64_t central_freq,
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uint64_t dco_freq,
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unsigned int divider)
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{
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uint64_t deviation;
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bool found = false;
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deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
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central_freq);
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/* positive deviation */
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if (dco_freq >= central_freq) {
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if (deviation < SKL_MAX_PDEVIATION &&
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deviation < ctx->min_deviation) {
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ctx->min_deviation = deviation;
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ctx->central_freq = central_freq;
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ctx->dco_freq = dco_freq;
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ctx->p = divider;
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#if 0
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found = true;
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#endif
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}
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/* we can't improve a 0 deviation */
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if (deviation == 0)
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return true;
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/* negative deviation */
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} else if (deviation < SKL_MAX_NDEVIATION &&
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deviation < ctx->min_deviation) {
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ctx->min_deviation = deviation;
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ctx->central_freq = central_freq;
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ctx->dco_freq = dco_freq;
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ctx->p = divider;
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#if 0
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found = true;
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#endif
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}
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if (found) {
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printf("Divider %d\n", divider);
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printf("Deviation %"PRIu64"\n", deviation);
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printf("dco_freq: %"PRIu64", dco_central_freq %"PRIu64"\n",
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dco_freq, central_freq);
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}
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return false;
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}
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static void skl_wrpll_get_multipliers(unsigned int p,
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unsigned int *p0 /* out */,
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unsigned int *p1 /* out */,
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unsigned int *p2 /* out */)
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{
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/* even dividers */
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if (p % 2 == 0) {
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unsigned int half = p / 2;
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if (half == 1 || half == 2 || half == 3 || half == 5) {
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*p0 = 2;
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*p1 = 1;
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*p2 = half;
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} else if (half % 2 == 0) {
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*p0 = 2;
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*p1 = half / 2;
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*p2 = 2;
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} else if (half % 3 == 0) {
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*p0 = 3;
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*p1 = half / 3;
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*p2 = 2;
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} else if (half % 7 == 0) {
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*p0 = 7;
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*p1 = half / 7;
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*p2 = 2;
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}
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} else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
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*p0 = 3;
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*p1 = 1;
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*p2 = p / 3;
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} else if (p == 5 || p == 7) {
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*p0 = p;
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*p1 = 1;
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*p2 = 1;
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} else if (p == 15) {
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*p0 = 3;
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*p1 = 1;
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*p2 = 5;
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} else if (p == 21) {
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*p0 = 7;
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*p1 = 1;
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*p2 = 3;
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} else if (p == 35) {
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*p0 = 7;
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*p1 = 1;
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*p2 = 5;
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}
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}
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static void test_multipliers(void)
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{
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static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
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24, 28, 30, 32, 36, 40, 42, 44,
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48, 52, 54, 56, 60, 64, 66, 68,
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70, 72, 76, 78, 80, 84, 88, 90,
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92, 96, 98 };
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static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
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static const struct {
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const int *list;
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int n_dividers;
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} dividers[] = {
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{ even_dividers, ARRAY_SIZE(even_dividers) },
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{ odd_dividers, ARRAY_SIZE(odd_dividers) },
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};
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unsigned int d, i;
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for (d = 0; d < ARRAY_SIZE(dividers); d++) {
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for (i = 0; i < dividers[d].n_dividers; i++) {
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unsigned int p = dividers[d].list[i];
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unsigned p0, p1, p2;
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p0 = p1 = p2 = 0;
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skl_wrpll_get_multipliers(p, &p0, &p1, &p2);
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assert(p0);
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assert(p1);
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assert(p2);
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assert(p == p0 * p1 * p2);
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}
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}
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}
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static bool
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skl_ddi_calculate_wrpll2(int clock /* in Hz */,
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struct skl_wrpll_params *wrpll_params)
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{
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uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
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uint64_t dco_central_freq[3] = {8400000000ULL,
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9000000000ULL,
|
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9600000000ULL};
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static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
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24, 28, 30, 32, 36, 40, 42, 44,
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48, 52, 54, 56, 60, 64, 66, 68,
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70, 72, 76, 78, 80, 84, 88, 90,
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92, 96, 98 };
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static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
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static const struct {
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const int *list;
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int n_dividers;
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} dividers[] = {
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{ even_dividers, ARRAY_SIZE(even_dividers) },
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{ odd_dividers, ARRAY_SIZE(odd_dividers) },
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};
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struct skl_wrpll_context ctx;
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unsigned int dco, d, i;
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unsigned int p0, p1, p2;
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skl_wrpll_context_init(&ctx);
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|
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for (d = 0; d < ARRAY_SIZE(dividers); d++) {
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for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
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for (i = 0; i < dividers[d].n_dividers; i++) {
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unsigned int p = dividers[d].list[i];
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uint64_t dco_freq = p * afe_clock;
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if (skl_wrpll_try_divider(&ctx,
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dco_central_freq[dco],
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dco_freq,
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p))
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goto skip_remaining_dividers;
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}
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}
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skip_remaining_dividers:
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/*
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* If a solution is found with an even divider, prefer
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* this one.
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*/
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if (d == 0 && ctx.p)
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break;
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}
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|
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if (!ctx.p)
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return false;
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skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
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|
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/* for this unit test only */
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wrpll_params->central_freq_hz = ctx.central_freq;
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wrpll_params->p0 = p0;
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wrpll_params->p1 = p1;
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wrpll_params->p2 = p2;
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return true;
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}
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|
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static const struct {
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uint32_t clock; /* in Hz */
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} modes[] = {
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{ 19750000 },
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{ 20000000 },
|
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{ 21000000 },
|
|
{ 21912000 },
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{ 22000000 },
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{ 23000000 },
|
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{ 23500000 },
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{ 23750000 },
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{ 24000000 },
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{ 25000000 },
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{ 25175000 },
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{ 25200000 },
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{ 26000000 },
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|
{ 27000000 },
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{ 27027000 },
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{ 27500000 },
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{ 28000000 },
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{ 28320000 },
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{ 28322000 },
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{ 28750000 },
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{ 29000000 },
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{ 29750000 },
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{ 30000000 },
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{ 30750000 },
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{ 31000000 },
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{ 31500000 },
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{ 32000000 },
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{ 32500000 },
|
|
{ 33000000 },
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|
{ 34000000 },
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|
{ 35000000 },
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|
{ 35500000 },
|
|
{ 36000000 },
|
|
{ 36750000 },
|
|
{ 37000000 },
|
|
{ 37762500 },
|
|
{ 37800000 },
|
|
{ 38000000 },
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{ 38250000 },
|
|
{ 39000000 },
|
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{ 40000000 },
|
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{ 40500000 },
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|
{ 40541000 },
|
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{ 40750000 },
|
|
{ 41000000 },
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{ 41500000 },
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{ 41540000 },
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{ 42000000 },
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{ 42500000 },
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{ 43000000 },
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{ 43163000 },
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{ 44000000 },
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{ 44900000 },
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{ 45000000 },
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{ 45250000 },
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{ 46000000 },
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{ 46750000 },
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{ 47000000 },
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{ 48000000 },
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{ 49000000 },
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{ 49500000 },
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{ 50000000 },
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{ 50500000 },
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{ 51000000 },
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{ 52000000 },
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{ 52406000 },
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{ 53000000 },
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{ 54000000 },
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{ 54054000 },
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{ 54500000 },
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{ 55000000 },
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{ 56000000 },
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{ 56250000 },
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{ 56750000 },
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{ 57000000 },
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{ 58000000 },
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{ 58250000 },
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{ 58750000 },
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{ 59000000 },
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{ 59341000 },
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{ 59400000 },
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{ 60000000 },
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{ 60500000 },
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{ 61000000 },
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{ 62000000 },
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{ 62250000 },
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{ 63000000 },
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{ 63500000 },
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{ 64000000 },
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{ 65000000 },
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{ 65250000 },
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{ 65500000 },
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{ 66000000 },
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{ 66667000 },
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{ 66750000 },
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{ 67000000 },
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{ 67750000 },
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{ 68000000 },
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{ 68179000 },
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{ 68250000 },
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{ 69000000 },
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{ 70000000 },
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{ 71000000 },
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{ 72000000 },
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{ 73000000 },
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{ 74000000 },
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{ 74176000 },
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{ 74250000 },
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{ 74481000 },
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{ 74500000 },
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{ 75000000 },
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{ 75250000 },
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{ 76000000 },
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{ 77000000 },
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{ 78000000 },
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{ 78750000 },
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{ 79000000 },
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{ 79500000 },
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{ 80000000 },
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{ 81000000 },
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{ 81081000 },
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{ 81624000 },
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{ 82000000 },
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{ 83950000 },
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{ 84000000 },
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{ 84750000 },
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{ 85000000 },
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{ 85250000 },
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{ 85750000 },
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{ 86000000 },
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{ 87000000 },
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{ 88000000 },
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{ 88500000 },
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{ 89000000 },
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{ 89012000 },
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{ 89100000 },
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{ 90000000 },
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{ 91000000 },
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{ 92000000 },
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{ 93000000 },
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{ 94000000 },
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{ 94500000 },
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{ 95000000 },
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{ 95654000 },
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{ 95750000 },
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{ 97000000 },
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{ 97750000 },
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{ 98000000 },
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{ 99000000 },
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{ 99750000 },
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{ 100000000 },
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{ 100500000 },
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{ 101000000 },
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{ 101250000 },
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{ 102250000 },
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{ 103000000 },
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{ 110013000 },
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{ 110250000 },
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{ 117500000 },
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{ 118000000 },
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{ 119000000 },
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{ 119500000 },
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{ 119651000 },
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{ 120000000 },
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{ 121000000 },
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{ 121250000 },
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{ 122000000 },
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{ 125250000 },
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{ 125750000 },
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{ 128000000 },
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{ 129000000 },
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{ 129859000 },
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{ 130250000 },
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{ 131000000 },
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{ 131500000 },
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{ 131850000 },
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{ 132000000 },
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{ 132750000 },
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{ 133000000 },
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{ 133330000 },
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{ 134000000 },
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{ 135000000 },
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{ 135250000 },
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{ 136000000 },
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{ 137000000 },
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{ 138000000 },
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{ 138500000 },
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{ 138750000 },
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{ 139000000 },
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{ 139050000 },
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{ 139054000 },
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{ 140000000 },
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{ 141000000 },
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{ 141500000 },
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{ 142000000 },
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{ 143000000 },
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{ 143472000 },
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{ 144000000 },
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{ 146250000 },
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{ 147000000 },
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{ 147891000 },
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{ 148000000 },
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{ 148250000 },
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{ 148352000 },
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{ 148500000 },
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{ 149000000 },
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{ 150000000 },
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{ 151000000 },
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{ 152000000 },
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{ 152280000 },
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{ 153000000 },
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{ 154000000 },
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{ 155000000 },
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{ 155250000 },
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{ 155750000 },
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{ 156000000 },
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{ 157000000 },
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{ 157500000 },
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{ 158000000 },
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{ 158250000 },
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{ 159500000 },
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{ 160000000 },
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{ 161000000 },
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{ 162000000 },
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{ 162162000 },
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{ 162500000 },
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{ 163000000 },
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{ 166000000 },
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{ 167000000 },
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{ 168000000 },
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{ 169000000 },
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{ 169128000 },
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{ 169500000 },
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{ 170000000 },
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{ 171000000 },
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{ 172000000 },
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{ 172750000 },
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{ 178000000 },
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{ 178500000 },
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{ 179500000 },
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{ 180000000 },
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{ 181000000 },
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{ 182000000 },
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{ 184750000 },
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{ 190000000 },
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{ 190960000 },
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{ 191000000 },
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{ 192000000 },
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{ 192250000 },
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{ 193000000 },
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{ 193250000 },
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{ 194000000 },
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{ 194208000 },
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{ 195000000 },
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{ 196000000 },
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{ 197000000 },
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{ 197750000 },
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{ 198000000 },
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{ 198500000 },
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{ 199000000 },
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{ 200000000 },
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{ 201000000 },
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{ 202000000 },
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{ 202500000 },
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{ 203000000 },
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{ 204000000 },
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{ 204750000 },
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{ 205000000 },
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{ 206000000 },
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{ 207000000 },
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{ 207500000 },
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{ 208000000 },
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{ 208900000 },
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{ 209000000 },
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{ 209250000 },
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{ 210000000 },
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{ 211000000 },
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{ 212000000 },
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{ 213000000 },
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{ 213750000 },
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{ 214000000 },
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{ 214750000 },
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{ 215000000 },
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{ 216000000 },
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{ 217000000 },
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{ 218000000 },
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{ 218250000 },
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{ 218750000 },
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{ 219000000 },
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{ 220000000 },
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{ 220640000 },
|
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{ 220750000 },
|
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{ 221000000 },
|
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{ 222000000 },
|
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{ 222525000 },
|
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{ 222750000 },
|
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{ 227000000 },
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{ 230250000 },
|
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{ 233500000 },
|
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{ 235000000 },
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{ 238000000 },
|
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{ 241500000 },
|
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{ 245250000 },
|
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{ 247750000 },
|
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{ 253250000 },
|
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{ 256250000 },
|
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{ 262500000 },
|
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{ 267250000 },
|
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{ 268500000 },
|
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{ 270000000 },
|
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{ 272500000 },
|
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{ 273750000 },
|
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{ 280750000 },
|
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{ 281250000 },
|
|
{ 286000000 },
|
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{ 291750000 },
|
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{ 296703000 },
|
|
{ 297000000 },
|
|
{ 298000000 },
|
|
};
|
|
|
|
struct test_ops {
|
|
bool (*compute)(int clock, struct skl_wrpll_params *params);
|
|
} tests[] = {
|
|
{ .compute = skl_ddi_calculate_wrpll1 },
|
|
{ .compute = skl_ddi_calculate_wrpll2 },
|
|
};
|
|
|
|
static void test_run(struct test_ops *test)
|
|
{
|
|
unsigned int m;
|
|
unsigned p_odd_even[2] = { 0, 0 };
|
|
igt_stats_t stats;
|
|
|
|
igt_stats_init_with_size(&stats, ARRAY_SIZE(modes));
|
|
igt_stats_set_population(&stats, true);
|
|
|
|
for (m = 0; m < ARRAY_SIZE(modes); m++) {
|
|
struct skl_wrpll_params params = {};
|
|
int clock = modes[m].clock;
|
|
unsigned int p;
|
|
|
|
if (!test->compute(clock, ¶ms)) {
|
|
fprintf(stderr, "Couldn't compute divider for %dHz\n",
|
|
clock);
|
|
continue;
|
|
}
|
|
|
|
p = params.p0 * params.p1 * params.p2;
|
|
|
|
/*
|
|
* make sure we respect the +1%/-6% contraint around the
|
|
* central frequency
|
|
*/
|
|
{
|
|
uint64_t dco_freq = (uint64_t)p * clock * 5;
|
|
uint64_t central_freq = params.central_freq_hz;
|
|
uint64_t deviation;
|
|
uint64_t diff;
|
|
|
|
diff = abs_diff(dco_freq, central_freq);
|
|
deviation = div64_u64(10000 * diff, central_freq);
|
|
|
|
igt_stats_push(&stats, deviation);
|
|
|
|
if (dco_freq > central_freq) {
|
|
if (deviation > 100)
|
|
printf("failed constraint for %dHz "
|
|
"deviation=%"PRIu64"\n", clock,
|
|
deviation);
|
|
} else if (deviation > 600)
|
|
printf("failed constraint for %dHz "
|
|
"deviation=%"PRIu64"\n", clock,
|
|
deviation);
|
|
}
|
|
|
|
/*
|
|
* count how many even/odd dividers we have through the whole
|
|
* list of tested frequencies
|
|
*/
|
|
{
|
|
p_odd_even[p % 2]++;
|
|
}
|
|
}
|
|
|
|
printf("even/odd dividers: %d/%d\n", p_odd_even[0], p_odd_even[1]);
|
|
printf("mean central freq deviation: %.2lf\n",
|
|
igt_stats_get_mean(&stats));
|
|
|
|
igt_stats_fini(&stats);
|
|
}
|
|
|
|
int main(int argc, char **argv)
|
|
{
|
|
unsigned int t;
|
|
|
|
test_multipliers();
|
|
|
|
for (t = 0; t < ARRAY_SIZE(tests); t++) {
|
|
printf("=== Testing algorithm #%d\n", t + 1);
|
|
test_run(&tests[t]);
|
|
}
|
|
|
|
|
|
return 0;
|
|
}
|