mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-08 16:36:14 +00:00
10c6ad3805
This is to add fill operation using GPGPU pipeline which is similar to current media fill. This can be used to simply verify GPGPU pipeline and help to enable it on newer HW, currently it works on Gen7 only and will add support on later platform. Now this sets very simply thread group dispatch for one thread per thread group on SIMD16 dispatch. So the fill shader just uses thread group ID for buffer offset. v2: No new fill func typedef but adapt to igt_fillfunc_t. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
509 lines
12 KiB
C
509 lines
12 KiB
C
#include <intel_bufmgr.h>
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#include <i915_drm.h>
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#include "media_fill.h"
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#include "gen7_media.h"
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#include "intel_reg.h"
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#include "drmtest.h"
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#include <assert.h>
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static const uint32_t media_kernel[][4] = {
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{ 0x00400001, 0x20200231, 0x00000020, 0x00000000 },
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{ 0x00600001, 0x20800021, 0x008d0000, 0x00000000 },
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{ 0x00200001, 0x20800021, 0x00450040, 0x00000000 },
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{ 0x00000001, 0x20880061, 0x00000000, 0x000f000f },
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{ 0x00800001, 0x20a00021, 0x00000020, 0x00000000 },
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{ 0x00800001, 0x20e00021, 0x00000020, 0x00000000 },
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{ 0x00800001, 0x21200021, 0x00000020, 0x00000000 },
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{ 0x00800001, 0x21600021, 0x00000020, 0x00000000 },
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{ 0x05800031, 0x24001ca8, 0x00000080, 0x120a8000 },
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{ 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 },
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{ 0x07800031, 0x20001ca8, 0x00000e00, 0x82000010 },
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};
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/* shaders/gpgpu/gpgpu_fill.gxa */
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static const uint32_t gpgpu_kernel[][4] = {
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{ 0x00400001, 0x20200231, 0x00000020, 0x00000000 },
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{ 0x00000041, 0x20400c21, 0x00000004, 0x00000010 },
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{ 0x00000001, 0x20440021, 0x00000018, 0x00000000 },
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{ 0x00600001, 0x20800021, 0x008d0000, 0x00000000 },
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{ 0x00200001, 0x20800021, 0x00450040, 0x00000000 },
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{ 0x00000001, 0x20880061, 0x00000000, 0x0000000f },
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{ 0x00800001, 0x20a00021, 0x00000020, 0x00000000 },
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{ 0x00800001, 0x20e00021, 0x00000020, 0x00000000 },
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{ 0x00800001, 0x21200021, 0x00000020, 0x00000000 },
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{ 0x00800001, 0x21600021, 0x00000020, 0x00000000 },
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{ 0x05800031, 0x24001ca8, 0x00000080, 0x120a8000 },
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{ 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 },
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{ 0x07800031, 0x20001ca8, 0x00000e00, 0x82000010 },
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};
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static uint32_t
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batch_used(struct intel_batchbuffer *batch)
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{
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return batch->ptr - batch->buffer;
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}
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static uint32_t
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batch_align(struct intel_batchbuffer *batch, uint32_t align)
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{
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uint32_t offset = batch_used(batch);
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offset = ALIGN(offset, align);
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batch->ptr = batch->buffer + offset;
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return offset;
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}
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static void *
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batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
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{
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uint32_t offset = batch_align(batch, align);
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batch->ptr += size;
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return memset(batch->buffer + offset, 0, size);
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}
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static uint32_t
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batch_offset(struct intel_batchbuffer *batch, void *ptr)
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{
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return (uint8_t *)ptr - batch->buffer;
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}
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static uint32_t
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batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
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{
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return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
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}
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static void
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gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
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{
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int ret;
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ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
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if (ret == 0)
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ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
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NULL, 0, 0, 0);
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igt_assert(ret == 0);
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}
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static uint32_t
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gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
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uint8_t color)
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{
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uint8_t *curbe_buffer;
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uint32_t offset;
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curbe_buffer = batch_alloc(batch, sizeof(uint32_t) * 8, 64);
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offset = batch_offset(batch, curbe_buffer);
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*curbe_buffer = color;
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return offset;
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}
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static uint32_t
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gen7_fill_surface_state(struct intel_batchbuffer *batch,
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struct igt_buf *buf,
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uint32_t format,
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int is_dst)
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{
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struct gen7_surface_state *ss;
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uint32_t write_domain, read_domain, offset;
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int ret;
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if (is_dst) {
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write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
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} else {
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write_domain = 0;
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read_domain = I915_GEM_DOMAIN_SAMPLER;
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}
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ss = batch_alloc(batch, sizeof(*ss), 64);
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offset = batch_offset(batch, ss);
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ss->ss0.surface_type = GEN7_SURFACE_2D;
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ss->ss0.surface_format = format;
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ss->ss0.render_cache_read_write = 1;
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if (buf->tiling == I915_TILING_X)
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ss->ss0.tiled_mode = 2;
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else if (buf->tiling == I915_TILING_Y)
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ss->ss0.tiled_mode = 3;
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ss->ss1.base_addr = buf->bo->offset;
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ret = drm_intel_bo_emit_reloc(batch->bo,
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batch_offset(batch, ss) + 4,
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buf->bo, 0,
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read_domain, write_domain);
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igt_assert(ret == 0);
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ss->ss2.height = igt_buf_height(buf) - 1;
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ss->ss2.width = igt_buf_width(buf) - 1;
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ss->ss3.pitch = buf->stride - 1;
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ss->ss7.shader_chanel_select_r = 4;
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ss->ss7.shader_chanel_select_g = 5;
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ss->ss7.shader_chanel_select_b = 6;
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ss->ss7.shader_chanel_select_a = 7;
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return offset;
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}
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static uint32_t
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gen7_fill_binding_table(struct intel_batchbuffer *batch,
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struct igt_buf *dst)
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{
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uint32_t *binding_table, offset;
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binding_table = batch_alloc(batch, 32, 64);
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offset = batch_offset(batch, binding_table);
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binding_table[0] = gen7_fill_surface_state(batch, dst, GEN7_SURFACEFORMAT_R8_UNORM, 1);
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return offset;
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}
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static uint32_t
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gen7_fill_media_kernel(struct intel_batchbuffer *batch,
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const uint32_t kernel[][4],
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size_t size)
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{
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uint32_t offset;
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offset = batch_copy(batch, kernel, size, 64);
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return offset;
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}
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static uint32_t
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gen7_fill_interface_descriptor(struct intel_batchbuffer *batch, struct igt_buf *dst,
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const uint32_t kernel[][4], size_t size)
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{
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struct gen7_interface_descriptor_data *idd;
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uint32_t offset;
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uint32_t binding_table_offset, kernel_offset;
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binding_table_offset = gen7_fill_binding_table(batch, dst);
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kernel_offset = gen7_fill_media_kernel(batch, kernel, size);
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idd = batch_alloc(batch, sizeof(*idd), 64);
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offset = batch_offset(batch, idd);
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idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
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idd->desc1.single_program_flow = 1;
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idd->desc1.floating_point_mode = GEN7_FLOATING_POINT_IEEE_754;
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idd->desc2.sampler_count = 0; /* 0 samplers used */
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idd->desc2.sampler_state_pointer = 0;
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idd->desc3.binding_table_entry_count = 0;
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idd->desc3.binding_table_pointer = (binding_table_offset >> 5);
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idd->desc4.constant_urb_entry_read_offset = 0;
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idd->desc4.constant_urb_entry_read_length = 1; /* grf 1 */
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return offset;
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}
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static void
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gen7_emit_state_base_address(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2));
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/* general */
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OUT_BATCH(0);
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/* surface */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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/* dynamic */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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/* indirect */
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OUT_BATCH(0);
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/* instruction */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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/* general/dynamic/indirect/instruction access Bound */
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OUT_BATCH(0);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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}
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static void
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gen7_emit_vfe_state(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_MEDIA_VFE_STATE | (8 - 2));
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/* scratch buffer */
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OUT_BATCH(0);
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/* number of threads & urb entries */
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OUT_BATCH(1 << 16 |
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2 << 8);
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OUT_BATCH(0);
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/* urb entry size & curbe size */
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OUT_BATCH(2 << 16 | /* in 256 bits unit */
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2); /* in 256 bits unit */
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/* scoreboard */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen7_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer)
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{
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OUT_BATCH(GEN7_MEDIA_CURBE_LOAD | (4 - 2));
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OUT_BATCH(0);
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/* curbe total data length */
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OUT_BATCH(64);
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/* curbe data start address, is relative to the dynamics base address */
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OUT_BATCH(curbe_buffer);
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}
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static void
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gen7_emit_interface_descriptor_load(struct intel_batchbuffer *batch, uint32_t interface_descriptor)
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{
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OUT_BATCH(GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
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OUT_BATCH(0);
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/* interface descriptor data length */
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OUT_BATCH(sizeof(struct gen7_interface_descriptor_data));
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/* interface descriptor address, is relative to the dynamics base address */
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OUT_BATCH(interface_descriptor);
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}
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static void
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gen7_emit_media_objects(struct intel_batchbuffer *batch,
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unsigned x, unsigned y,
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unsigned width, unsigned height)
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{
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int i, j;
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for (i = 0; i < width / 16; i++) {
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for (j = 0; j < height / 16; j++) {
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OUT_BATCH(GEN7_MEDIA_OBJECT | (8 - 2));
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/* interface descriptor offset */
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OUT_BATCH(0);
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/* without indirect data */
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* scoreboard */
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* inline data (xoffset, yoffset) */
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OUT_BATCH(x + i * 16);
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OUT_BATCH(y + j * 16);
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}
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}
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}
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/*
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* This sets up the media pipeline,
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*
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* +---------------+ <---- 4096
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* | ^ |
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* | | |
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* | various |
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* | state |
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* | | |
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* |_______|_______| <---- 2048 + ?
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* | ^ |
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* | | |
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* | batch |
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* | commands |
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* | | |
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* | | |
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* +---------------+ <---- 0 + ?
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*
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*/
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#define BATCH_STATE_SPLIT 2048
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void
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gen7_media_fillfunc(struct intel_batchbuffer *batch,
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struct igt_buf *dst,
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unsigned x, unsigned y,
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unsigned width, unsigned height,
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uint8_t color)
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{
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uint32_t curbe_buffer, interface_descriptor;
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uint32_t batch_end;
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intel_batchbuffer_flush(batch);
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/* setup states */
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batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
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curbe_buffer = gen7_fill_curbe_buffer_data(batch, color);
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interface_descriptor = gen7_fill_interface_descriptor(batch, dst,
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media_kernel,
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sizeof(media_kernel));
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igt_assert(batch->ptr < &batch->buffer[4095]);
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/* media pipeline */
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batch->ptr = batch->buffer;
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OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
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gen7_emit_state_base_address(batch);
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gen7_emit_vfe_state(batch);
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gen7_emit_curbe_load(batch, curbe_buffer);
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gen7_emit_interface_descriptor_load(batch, interface_descriptor);
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gen7_emit_media_objects(batch, x, y, width, height);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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batch_end = batch_align(batch, 8);
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igt_assert(batch_end < BATCH_STATE_SPLIT);
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gen7_render_flush(batch, batch_end);
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intel_batchbuffer_reset(batch);
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}
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static void
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gen7_emit_vfe_state_gpgpu(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_MEDIA_VFE_STATE | (8 - 2));
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/* scratch buffer */
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OUT_BATCH(0);
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/* number of threads & urb entries */
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OUT_BATCH(1 << 16 | /* max num of threads */
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0 << 8 | /* num of URB entry */
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1 << 2); /* GPGPU mode */
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OUT_BATCH(0);
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/* urb entry size & curbe size */
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OUT_BATCH(0 << 16 | /* URB entry size in 256 bits unit */
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1); /* CURBE entry size in 256 bits unit */
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/* scoreboard */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen7_emit_gpgpu_walk(struct intel_batchbuffer *batch,
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unsigned x, unsigned y,
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unsigned width, unsigned height)
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{
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uint32_t x_dim, y_dim, tmp, right_mask;
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/*
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* Simply do SIMD16 based dispatch, so every thread uses
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* SIMD16 channels.
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*
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* Define our own thread group size, e.g 16x1 for every group, then
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* will have 1 thread each group in SIMD16 dispatch. So thread
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* width/height/depth are all 1.
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*
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* Then thread group X = width / 16 (aligned to 16)
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* thread group Y = height;
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*/
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x_dim = (width + 15) / 16;
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y_dim = height;
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tmp = width & 15;
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if (tmp == 0)
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right_mask = (1 << 16) - 1;
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else
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right_mask = (1 << tmp) - 1;
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OUT_BATCH(GEN7_GPGPU_WALKER | 9);
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/* interface descriptor offset */
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OUT_BATCH(0);
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/* SIMD size, thread w/h/d */
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OUT_BATCH(1 << 30 | /* SIMD16 */
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0 << 16 | /* depth:1 */
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0 << 8 | /* height:1 */
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0); /* width:1 */
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/* thread group X */
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OUT_BATCH(0);
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OUT_BATCH(x_dim);
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/* thread group Y */
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OUT_BATCH(0);
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OUT_BATCH(y_dim);
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/* thread group Z */
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OUT_BATCH(0);
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OUT_BATCH(1);
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/* right mask */
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OUT_BATCH(right_mask);
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/* bottom mask, height 1, always 0xffffffff */
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OUT_BATCH(0xffffffff);
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}
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void
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gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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struct igt_buf *dst,
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unsigned x, unsigned y,
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unsigned width, unsigned height,
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uint8_t color)
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{
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uint32_t curbe_buffer, interface_descriptor;
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uint32_t batch_end;
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intel_batchbuffer_flush(batch);
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/* setup states */
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batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
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/*
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* const buffer needs to fill for every thread, but as we have just 1 thread
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* per every group, so need only one curbe data.
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*
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* For each thread, just use thread group ID for buffer offset.
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*/
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curbe_buffer = gen7_fill_curbe_buffer_data(batch, color);
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interface_descriptor = gen7_fill_interface_descriptor(batch, dst,
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gpgpu_kernel,
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sizeof(gpgpu_kernel));
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igt_assert(batch->ptr < &batch->buffer[4095]);
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batch->ptr = batch->buffer;
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/* GPGPU pipeline */
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OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
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gen7_emit_state_base_address(batch);
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gen7_emit_vfe_state_gpgpu(batch);
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gen7_emit_curbe_load(batch, curbe_buffer);
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gen7_emit_interface_descriptor_load(batch, interface_descriptor);
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gen7_emit_gpgpu_walk(batch, x, y, width, height);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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batch_end = batch_align(batch, 8);
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igt_assert(batch_end < BATCH_STATE_SPLIT);
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gen7_render_flush(batch, batch_end);
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intel_batchbuffer_reset(batch);
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}
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