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https://github.com/tiagovignatti/intel-gpu-tools.git
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4fc76adf31
In Valleyview the DPLL and lane control registers are accessible only through side band fabric called DPIO. Added two tools to read and write registers residing in this space. v2: Moved the core read/write functions to lib/intel_dpio.c based on Ben's feedback Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
105 lines
3.1 KiB
C
105 lines
3.1 KiB
C
/*
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* Copyright © 2009 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifndef INTEL_GPU_TOOLS_H
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#define INTEL_GPU_TOOLS_H
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#include <stdint.h>
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#include <sys/types.h>
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#include <pciaccess.h>
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#include "intel_chipset.h"
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#include "intel_reg.h"
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#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
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extern void *mmio;
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void intel_get_mmio(struct pci_device *pci_dev);
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/* New style register access API */
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int intel_register_access_init(struct pci_device *pci_dev, int safe);
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void intel_register_access_fini(void);
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uint32_t intel_register_read(uint32_t reg);
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void intel_register_write(uint32_t reg, uint32_t val);
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/* Following functions are relevant only for SoCs like Valleyview */
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uint32_t intel_dpio_reg_read(uint32_t reg);
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void intel_dpio_reg_write(uint32_t reg, uint32_t val);
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#define INTEL_RANGE_RSVD (0<<0) /* Shouldn't be read or written */
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#define INTEL_RANGE_READ (1<<0)
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#define INTEL_RANGE_WRITE (1<<1)
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#define INTEL_RANGE_RW (INTEL_RANGE_READ | INTEL_RANGE_WRITE)
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#define INTEL_RANGE_END (1<<31)
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struct intel_register_range {
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uint32_t base;
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uint32_t size;
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uint32_t flags;
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};
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struct intel_register_map {
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struct intel_register_range *map;
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uint32_t top;
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uint32_t alignment_mask;
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};
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struct intel_register_map intel_get_register_map(uint32_t devid);
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struct intel_register_range *intel_get_register_range(struct intel_register_map map, uint32_t offset, int mode);
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static inline uint32_t
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INREG(uint32_t reg)
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{
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return *(volatile uint32_t *)((volatile char *)mmio + reg);
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}
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static inline void
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OUTREG(uint32_t reg, uint32_t val)
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{
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*(volatile uint32_t *)((volatile char *)mmio + reg) = val;
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}
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struct pci_device *intel_get_pci_device(void);
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uint32_t intel_get_drm_devid(int fd);
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int intel_gen(uint32_t devid);
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uint64_t intel_get_total_ram_mb(void);
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uint64_t intel_get_total_swap_mb(void);
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void intel_map_file(char *);
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enum pch_type {
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PCH_IBX,
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PCH_CPT,
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};
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extern enum pch_type pch;
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void intel_check_pch(void);
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#define HAS_CPT (pch == PCH_CPT)
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#endif /* INTEL_GPU_TOOLS_H */
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