Ville Syrjälä 4e696ff8c9 quick_dump: pass register offsets as int ...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[imre: fix s/regi/intreg/ typo]
Reviewed-by: Imre Deak <imre.deak@intel.com>

2014-06-03 22:19:42 +03:00

..

.gitignore

tools/quickdump: gitignore generated files

2013-07-10 15:35:13 +02:00

audio_config_haswell_plus.txt

quick_dump/bdw: dump audio configuration registers for Haswell and Broadwell

2013-11-06 09:39:41 -08:00

audio_debug_haswell_plus.txt

quick_dump/bdw: dump audio debug registers for Haswell and Broadwell

2013-11-06 09:39:41 -08:00

base_display.txt

quick_dump: A dump utility different than reg_dumper

2013-02-07 16:42:18 -08:00

base_interrupt.txt

quick_dump: A dump utility different than reg_dumper

2013-02-07 16:42:18 -08:00

base_other.txt

quick_dump: fix text file

2013-05-23 11:17:31 -07:00

base_power.txt

quick_dump: A dump utility different than reg_dumper

2013-02-07 16:42:18 -08:00

base_rings.txt

quick_dump: Add more ring registers

2013-05-22 15:54:53 -07:00

broadwell

quick_dump: gen8 private PAT

2014-03-19 10:14:57 -07:00

chipset_macro_wrap.c

quick_dump: Fix the danvet fallout.

2014-03-26 09:02:58 -07:00

chipset.i

igt/quickdump: vlv: dump FLISDSI regs too

2014-05-19 20:13:15 +03:00

gen6_other.txt

quick_dump: gen6 support

2013-02-07 16:42:18 -08:00

gen7_other.txt

quick_dump/gen7: Add other GFX_MODE registers

2014-02-02 10:48:54 +01:00

gen8_interrupt.txt

quick_dump/bdw: Just basic stuff for now

2013-11-06 09:39:41 -08:00

gen8_other.txt

quick_dump: gen8 private PAT

2014-03-19 10:14:57 -07:00

haswell

quick_dump/haswell: Add gen7 stuff + VECS_MODE

2014-02-02 10:48:54 +01:00

haswell_other.txt

quick_dump/haswell: Add gen7 stuff + VECS_MODE

2014-02-02 10:48:54 +01:00

ivybridge

quick_dump: gen7 support

2013-02-07 16:42:18 -08:00

Makefile.am

tools/quick_dump: Fix make distcheck

2014-03-28 17:54:58 +01:00

quick_dump.py

quick_dump: pass register offsets as int

2014-06-03 22:19:42 +03:00

reg_access.py

quick_dump: pass register offsets as int

2014-06-03 22:19:42 +03:00

sandybridge

quick_dump: gen6 support

2013-02-07 16:42:18 -08:00

valleyview

igt/quickdump: vlv: dump FLISDSI regs too

2014-05-19 20:13:15 +03:00

vlv_display.txt

fixup VLV reg offsets, add a few more

2013-04-16 13:41:23 -07:00

vlv_dpio.txt

quick_dump: more vlv dpio regs

2014-01-27 10:27:20 -08:00

vlv_dsi.txt

quick_dump: vlv mipi dsi register support

2013-06-07 11:35:27 -07:00

vlv_flisdsi.txt

igt/quickdump: vlv: dump FLISDSI regs too

2014-05-19 20:13:15 +03:00

vlv_power.txt

fixup VLV reg offsets, add a few more

2013-04-16 13:41:23 -07:00