mirror of
				https://github.com/tiagovignatti/intel-gpu-tools.git
				synced 2025-11-04 12:07:12 +00:00 
			
		
		
		
	Apply the new API to all call sites within the test suite using the following semantic patch: // Semantic patch for replacing drm_open_any* with arch-specific drm_open_driver* calls @@ identifier i =~ "\bdrm_open_any\b"; @@ - i() + drm_open_driver(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_master\b"; @@ - i() + drm_open_driver_master(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_render\b"; @@ - i() + drm_open_driver_render(DRIVER_INTEL) @@ identifier i =~ "\b__drm_open_any\b"; @@ - i() + __drm_open_driver(DRIVER_INTEL) Signed-off-by: Micah Fedke <micah.fedke@collabora.co.uk> Signed-off-by: Thomas Wood <thomas.wood@intel.com>
		
			
				
	
	
		
			161 lines
		
	
	
		
			4.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			161 lines
		
	
	
		
			4.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright © 2012 Intel Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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 * IN THE SOFTWARE.
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 *
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 * Authors:
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 *    Daniel Vetter <daniel.vetter@ffwll.ch>
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 *
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 */
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/** @file gem_unfence_active_buffers.c
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 *
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 * Testcase: Check for use-after free in the fence stealing code
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 *
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 * If we're stealing the fence of a active object where the active list is the
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 * only thing holding a reference, we need to be careful not to access the old
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 * object we're stealing the fence from after that reference has been dropped by
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 * retire_requests.
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 *
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 * Note that this needs slab poisoning enabled in the kernel to reliably hit the
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 * problem - the race window is too small.
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 */
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#include "igt.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include <stdbool.h>
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#include "drm.h"
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#include "intel_bufmgr.h"
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IGT_TEST_DESCRIPTION("Check for use-after-free in the fence stealing code.");
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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uint32_t devid;
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#define TEST_SIZE (1024*1024)
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#define TEST_STRIDE (4*1024)
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uint32_t data[TEST_SIZE/4];
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igt_simple_main
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{
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	int i, ret, fd, num_fences;
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	drm_intel_bo *busy_bo, *test_bo;
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	uint32_t tiling = I915_TILING_X;
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	igt_skip_on_simulation();
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	for (i = 0; i < 1024*256; i++)
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		data[i] = i;
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	fd = drm_open_driver(DRIVER_INTEL);
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	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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	devid = intel_get_drm_devid(fd);
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	batch = intel_batchbuffer_alloc(bufmgr, devid);
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	igt_info("filling ring\n");
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	busy_bo = drm_intel_bo_alloc(bufmgr, "busy bo bo", 16*1024*1024, 4096);
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	for (i = 0; i < 250; i++) {
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		BLIT_COPY_BATCH_START(0);
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		OUT_BATCH((3 << 24) | /* 32 bits */
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			  (0xcc << 16) | /* copy ROP */
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			  2*1024*4);
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		OUT_BATCH(0 << 16 | 1024);
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		OUT_BATCH((2048) << 16 | (2048));
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		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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		OUT_BATCH(0 << 16 | 0);
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		OUT_BATCH(2*1024*4);
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		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
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		ADVANCE_BATCH();
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		if (batch->gen >= 6) {
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			BEGIN_BATCH(3, 0);
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			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
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			OUT_BATCH(0);
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			OUT_BATCH(0);
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			ADVANCE_BATCH();
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		}
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	}
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	intel_batchbuffer_flush(batch);
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	num_fences = gem_available_fences(fd);
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	igt_info("creating havoc on %i fences\n", num_fences);
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	for (i = 0; i < num_fences*2; i++) {
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		test_bo = drm_intel_bo_alloc(bufmgr, "test_bo",
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					     TEST_SIZE, 4096);
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		ret = drm_intel_bo_set_tiling(test_bo, &tiling, TEST_STRIDE);
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		igt_assert(ret == 0);
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		drm_intel_bo_disable_reuse(test_bo);
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		BLIT_COPY_BATCH_START(0);
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		OUT_BATCH((3 << 24) | /* 32 bits */
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			  (0xcc << 16) | /* copy ROP */
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			  TEST_STRIDE);
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		OUT_BATCH(0 << 16 | 0);
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		OUT_BATCH((1) << 16 | (1));
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		OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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		OUT_BATCH(0 << 16 | 0);
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		OUT_BATCH(TEST_STRIDE);
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		OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
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		ADVANCE_BATCH();
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		intel_batchbuffer_flush(batch);
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		igt_info("test bo offset: %#lx\n", test_bo->offset);
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		drm_intel_bo_unreference(test_bo);
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	}
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	/* launch a few batchs to ensure the damaged slab objects get reused. */
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	for (i = 0; i < 10; i++) {
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		BLIT_COPY_BATCH_START(0);
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		OUT_BATCH((3 << 24) | /* 32 bits */
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			  (0xcc << 16) | /* copy ROP */
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			  2*1024*4);
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		OUT_BATCH(0 << 16 | 1024);
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		OUT_BATCH((1) << 16 | (1));
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		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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		OUT_BATCH(0 << 16 | 0);
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		OUT_BATCH(2*1024*4);
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		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
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		ADVANCE_BATCH();
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		if (batch->gen >= 8) {
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			BEGIN_BATCH(3, 0);
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			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
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			OUT_BATCH(0);
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			OUT_BATCH(0);
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			ADVANCE_BATCH();
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		}
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	}
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	intel_batchbuffer_flush(batch);
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}
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