mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-11-04 12:07:12 +00:00
c81d293aed
Apply the new API to all call sites within the test suite using the following semantic patch: // Semantic patch for replacing drm_open_any* with arch-specific drm_open_driver* calls @@ identifier i =~ "\bdrm_open_any\b"; @@ - i() + drm_open_driver(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_master\b"; @@ - i() + drm_open_driver_master(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_render\b"; @@ - i() + drm_open_driver_render(DRIVER_INTEL) @@ identifier i =~ "\b__drm_open_any\b"; @@ - i() + __drm_open_driver(DRIVER_INTEL) Signed-off-by: Micah Fedke <micah.fedke@collabora.co.uk> Signed-off-by: Thomas Wood <thomas.wood@intel.com>
412 lines
11 KiB
C
412 lines
11 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Chris Wilson <chris@chris-wilson.co.uk>
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "igt.h"
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/time.h>
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#include <pthread.h>
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#include "drm.h"
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#include "i915_drm.h"
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#define OBJECT_SIZE (1024*1024) /* restricted to 1MiB alignment on i915 fences */
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static double elapsed(const struct timeval *start,
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const struct timeval *end)
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{
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return (end->tv_sec - start->tv_sec) + 1e-6*(end->tv_usec - start->tv_usec);
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}
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static void performance(void)
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{
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int n, loop, count;
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int fd, num_fences;
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double linear[2], tiled[2];
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fd = drm_open_driver(DRIVER_INTEL);
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num_fences = gem_available_fences(fd);
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igt_require(num_fences > 0);
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for (count = 2; count < 4*num_fences; count *= 2) {
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struct timeval start, end;
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uint32_t handle[count];
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void *ptr[count];
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for (n = 0; n < count; n++) {
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handle[n] = gem_create(fd, OBJECT_SIZE);
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ptr[n] = gem_mmap(fd, handle[n], OBJECT_SIZE, PROT_READ | PROT_WRITE);
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igt_assert(ptr[n]);
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}
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gettimeofday(&start, NULL);
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for (loop = 0; loop < 1024; loop++) {
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for (n = 0; n < count; n++)
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memset(ptr[n], 0, OBJECT_SIZE);
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}
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gettimeofday(&end, NULL);
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linear[count != 2] = count * loop / elapsed(&start, &end);
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igt_info("Upload rate for %d linear surfaces: %7.3fMiB/s\n", count, linear[count != 2]);
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for (n = 0; n < count; n++)
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gem_set_tiling(fd, handle[n], I915_TILING_X, 1024);
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gettimeofday(&start, NULL);
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for (loop = 0; loop < 1024; loop++) {
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for (n = 0; n < count; n++)
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memset(ptr[n], 0, OBJECT_SIZE);
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}
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gettimeofday(&end, NULL);
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tiled[count != 2] = count * loop / elapsed(&start, &end);
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igt_info("Upload rate for %d tiled surfaces: %7.3fMiB/s\n", count, tiled[count != 2]);
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for (n = 0; n < count; n++) {
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munmap(ptr[n], OBJECT_SIZE);
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gem_close(fd, handle[n]);
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}
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}
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errno = 0;
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igt_assert(linear[1] > 0.75 * linear[0]);
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igt_assert(tiled[1] > 0.75 * tiled[0]);
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}
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struct thread_performance {
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pthread_t thread;
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int id, count, direction, loops;
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void **ptr;
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};
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static void *read_thread_performance(void *closure)
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{
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struct thread_performance *t = closure;
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uint32_t x = 0;
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int n, m;
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for (n = 0; n < t->loops; n++) {
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uint32_t *src = t->ptr[rand() % t->count];
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src += (rand() % 256) * 4096 / 4;
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for (m = 0; m < 4096/4; m++)
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x += src[m];
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}
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return (void *)(uintptr_t)x;
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}
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static void *write_thread_performance(void *closure)
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{
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struct thread_performance *t = closure;
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int n;
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for (n = 0; n < t->loops; n++) {
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uint32_t *dst = t->ptr[rand() % t->count];
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dst += (rand() % 256) * 4096 / 4;
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memset(dst, 0, 4096);
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}
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return NULL;
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}
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#define READ (1<<0)
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#define WRITE (1<<1)
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static const char *direction_string(unsigned mask)
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{
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switch (mask) {
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case READ: return "Download";
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case WRITE: return "Upload";
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case READ | WRITE: return "Combined";
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default: return "Unknown";
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}
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}
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static void thread_performance(unsigned mask)
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{
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const int loops = 4096;
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int n, count;
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int fd, num_fences;
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double linear[2], tiled[2];
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fd = drm_open_driver(DRIVER_INTEL);
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num_fences = gem_available_fences(fd);
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igt_require(num_fences > 0);
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for (count = 2; count < 4*num_fences; count *= 2) {
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const int nthreads = (mask & READ ? count : 0) + (mask & WRITE ? count : 0);
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struct timeval start, end;
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struct thread_performance readers[count];
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struct thread_performance writers[count];
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uint32_t handle[count];
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void *ptr[count];
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for (n = 0; n < count; n++) {
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handle[n] = gem_create(fd, OBJECT_SIZE);
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ptr[n] = gem_mmap(fd, handle[n], OBJECT_SIZE, PROT_READ | PROT_WRITE);
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igt_assert(ptr[n]);
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if (mask & READ) {
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readers[n].id = n;
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readers[n].direction = READ;
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readers[n].ptr = ptr;
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readers[n].count = count;
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readers[n].loops = loops;
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}
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if (mask & WRITE) {
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writers[n].id = count - n - 1;
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writers[n].direction = WRITE;
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writers[n].ptr = ptr;
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writers[n].count = count;
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writers[n].loops = loops;
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}
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}
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gettimeofday(&start, NULL);
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for (n = 0; n < count; n++) {
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if (mask & READ)
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pthread_create(&readers[n].thread, NULL, read_thread_performance, &readers[n]);
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if (mask & WRITE)
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pthread_create(&writers[n].thread, NULL, write_thread_performance, &writers[n]);
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}
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for (n = 0; n < count; n++) {
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if (mask & READ)
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pthread_join(readers[n].thread, NULL);
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if (mask & WRITE)
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pthread_join(writers[n].thread, NULL);
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}
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gettimeofday(&end, NULL);
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linear[count != 2] = nthreads * loops / elapsed(&start, &end) / (OBJECT_SIZE / 4096);
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igt_info("%s rate for %d linear surfaces, %d threads: %7.3fMiB/s\n", direction_string(mask), count, nthreads, linear[count != 2]);
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for (n = 0; n < count; n++)
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gem_set_tiling(fd, handle[n], I915_TILING_X, 1024);
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gettimeofday(&start, NULL);
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for (n = 0; n < count; n++) {
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if (mask & READ)
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pthread_create(&readers[n].thread, NULL, read_thread_performance, &readers[n]);
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if (mask & WRITE)
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pthread_create(&writers[n].thread, NULL, write_thread_performance, &writers[n]);
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}
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for (n = 0; n < count; n++) {
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if (mask & READ)
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pthread_join(readers[n].thread, NULL);
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if (mask & WRITE)
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pthread_join(writers[n].thread, NULL);
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}
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gettimeofday(&end, NULL);
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tiled[count != 2] = nthreads * loops / elapsed(&start, &end) / (OBJECT_SIZE / 4096);
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igt_info("%s rate for %d tiled surfaces, %d threads: %7.3fMiB/s\n", direction_string(mask), count, nthreads, tiled[count != 2]);
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for (n = 0; n < count; n++) {
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munmap(ptr[n], OBJECT_SIZE);
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gem_close(fd, handle[n]);
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}
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}
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errno = 0;
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igt_assert(linear[1] > 0.75 * linear[0]);
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igt_assert(tiled[1] > 0.75 * tiled[0]);
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}
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struct thread_contention {
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pthread_t thread;
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uint32_t handle;
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int loops, fd;
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};
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static void *no_contention(void *closure)
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{
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struct thread_contention *t = closure;
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int n;
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for (n = 0; n < t->loops; n++) {
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uint32_t *ptr = gem_mmap(t->fd, t->handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
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igt_assert(ptr);
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memset(ptr + (rand() % 256) * 4096 / 4, 0, 4096);
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munmap(ptr, OBJECT_SIZE);
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}
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return NULL;
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}
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static void *wc_mmap(void *closure)
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{
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struct thread_contention *t = closure;
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int n;
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for (n = 0; n < t->loops; n++) {
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uint32_t *ptr = gem_mmap__wc(t->fd, t->handle, 0, OBJECT_SIZE, PROT_READ | PROT_WRITE);
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igt_assert(ptr);
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memset(ptr + (rand() % 256) * 4096 / 4, 0, 4096);
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munmap(ptr, OBJECT_SIZE);
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}
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return NULL;
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}
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static void thread_contention(void)
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{
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const int loops = 4096;
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int n, count;
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int fd, num_fences;
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double linear[2], tiled[2];
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fd = drm_open_driver(DRIVER_INTEL);
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num_fences = gem_available_fences(fd);
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igt_require(num_fences > 0);
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for (count = 1; count < 4*num_fences; count *= 2) {
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struct timeval start, end;
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struct thread_contention threads[count];
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for (n = 0; n < count; n++) {
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threads[n].handle = gem_create(fd, OBJECT_SIZE);
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threads[n].loops = loops;
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threads[n].fd = fd;
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}
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gettimeofday(&start, NULL);
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for (n = 0; n < count; n++)
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pthread_create(&threads[n].thread, NULL, no_contention, &threads[n]);
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for (n = 0; n < count; n++)
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pthread_join(threads[n].thread, NULL);
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gettimeofday(&end, NULL);
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linear[count != 2] = count * loops / elapsed(&start, &end) / (OBJECT_SIZE / 4096);
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igt_info("Contended upload rate for %d linear threads: %7.3fMiB/s\n", count, linear[count != 2]);
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for (n = 0; n < count; n++)
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gem_set_tiling(fd, threads[n].handle, I915_TILING_X, 1024);
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gettimeofday(&start, NULL);
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for (n = 0; n < count; n++)
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pthread_create(&threads[n].thread, NULL, no_contention, &threads[n]);
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for (n = 0; n < count; n++)
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pthread_join(threads[n].thread, NULL);
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gettimeofday(&end, NULL);
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tiled[count != 2] = count * loops / elapsed(&start, &end) / (OBJECT_SIZE / 4096);
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igt_info("Contended upload rate for %d tiled threads: %7.3fMiB/s\n", count, tiled[count != 2]);
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for (n = 0; n < count; n++) {
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gem_close(fd, threads[n].handle);
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}
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}
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errno = 0;
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igt_assert(linear[1] > 0.75 * linear[0]);
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igt_assert(tiled[1] > 0.75 * tiled[0]);
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}
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static void wc_contention(void)
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{
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const int loops = 4096;
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int n, count;
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int fd, num_fences;
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double linear[2], tiled[2];
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fd = drm_open_driver(DRIVER_INTEL);
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gem_require_mmap_wc(fd);
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num_fences = gem_available_fences(fd);
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igt_require(num_fences > 0);
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for (count = 1; count < 4*num_fences; count *= 2) {
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struct timeval start, end;
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struct thread_contention threads[count];
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for (n = 0; n < count; n++) {
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threads[n].handle = gem_create(fd, OBJECT_SIZE);
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threads[n].loops = loops;
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threads[n].fd = fd;
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}
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gettimeofday(&start, NULL);
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for (n = 0; n < count; n++)
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pthread_create(&threads[n].thread, NULL, wc_mmap, &threads[n]);
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for (n = 0; n < count; n++)
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pthread_join(threads[n].thread, NULL);
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gettimeofday(&end, NULL);
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linear[count != 2] = count * loops / elapsed(&start, &end) / (OBJECT_SIZE / 4096);
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igt_info("Contended upload rate for %d linear threads/wc: %7.3fMiB/s\n", count, linear[count != 2]);
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for (n = 0; n < count; n++)
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gem_set_tiling(fd, threads[n].handle, I915_TILING_X, 1024);
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gettimeofday(&start, NULL);
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for (n = 0; n < count; n++)
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pthread_create(&threads[n].thread, NULL, wc_mmap, &threads[n]);
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for (n = 0; n < count; n++)
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pthread_join(threads[n].thread, NULL);
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gettimeofday(&end, NULL);
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tiled[count != 2] = count * loops / elapsed(&start, &end) / (OBJECT_SIZE / 4096);
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igt_info("Contended upload rate for %d tiled threads/wc: %7.3fMiB/s\n", count, tiled[count != 2]);
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for (n = 0; n < count; n++) {
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gem_close(fd, threads[n].handle);
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}
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}
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errno = 0;
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igt_assert(linear[1] > 0.75 * linear[0]);
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igt_assert(tiled[1] > 0.75 * tiled[0]);
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}
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igt_main
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{
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igt_skip_on_simulation();
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igt_subtest("performance")
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performance();
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igt_subtest("thread-contention")
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thread_contention();
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igt_subtest("wc-contention")
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wc_contention();
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igt_subtest("thread-performance-read")
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thread_performance(READ);
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igt_subtest("thread-performance-write")
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thread_performance(WRITE);
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igt_subtest("thread-performance-both")
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thread_performance(READ | WRITE);
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}
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