mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-11-04 12:07:12 +00:00
c81d293aed
Apply the new API to all call sites within the test suite using the following semantic patch: // Semantic patch for replacing drm_open_any* with arch-specific drm_open_driver* calls @@ identifier i =~ "\bdrm_open_any\b"; @@ - i() + drm_open_driver(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_master\b"; @@ - i() + drm_open_driver_master(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_render\b"; @@ - i() + drm_open_driver_render(DRIVER_INTEL) @@ identifier i =~ "\b__drm_open_any\b"; @@ - i() + __drm_open_driver(DRIVER_INTEL) Signed-off-by: Micah Fedke <micah.fedke@collabora.co.uk> Signed-off-by: Thomas Wood <thomas.wood@intel.com>
487 lines
12 KiB
C
487 lines
12 KiB
C
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "igt.h"
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <errno.h>
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#include <drm.h>
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#ifndef I915_PARAM_CMD_PARSER_VERSION
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#define I915_PARAM_CMD_PARSER_VERSION 28
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#endif
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static int __gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
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{
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if (drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, execbuf))
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return -errno;
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return 0;
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}
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static void exec_batch_patched(int fd, uint32_t cmd_bo, uint32_t *cmds,
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int size, int patch_offset, uint64_t expected_value)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 objs[2];
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struct drm_i915_gem_relocation_entry reloc[1];
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uint32_t target_bo = gem_create(fd, 4096);
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uint64_t actual_value = 0;
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gem_write(fd, cmd_bo, 0, cmds, size);
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reloc[0].offset = patch_offset;
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reloc[0].delta = 0;
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reloc[0].target_handle = target_bo;
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reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
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reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
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reloc[0].presumed_offset = 0;
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objs[0].handle = target_bo;
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objs[0].relocation_count = 0;
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objs[0].relocs_ptr = 0;
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objs[0].alignment = 0;
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objs[0].offset = 0;
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objs[0].flags = 0;
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objs[0].rsvd1 = 0;
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objs[0].rsvd2 = 0;
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objs[1].handle = cmd_bo;
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objs[1].relocation_count = 1;
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objs[1].relocs_ptr = (uintptr_t)reloc;
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objs[1].alignment = 0;
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objs[1].offset = 0;
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objs[1].flags = 0;
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objs[1].rsvd1 = 0;
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objs[1].rsvd2 = 0;
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execbuf.buffers_ptr = (uintptr_t)objs;
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execbuf.buffer_count = 2;
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execbuf.batch_start_offset = 0;
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execbuf.batch_len = size;
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execbuf.cliprects_ptr = 0;
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execbuf.num_cliprects = 0;
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execbuf.DR1 = 0;
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execbuf.DR4 = 0;
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execbuf.flags = I915_EXEC_RENDER;
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i915_execbuffer2_set_context_id(execbuf, 0);
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execbuf.rsvd2 = 0;
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gem_execbuf(fd, &execbuf);
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gem_sync(fd, cmd_bo);
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gem_read(fd,target_bo, 0, &actual_value, sizeof(actual_value));
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igt_assert_eq(expected_value, actual_value);
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gem_close(fd, target_bo);
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}
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static int __exec_batch(int fd, uint32_t cmd_bo, uint32_t *cmds,
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int size, int ring)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 objs[1];
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gem_write(fd, cmd_bo, 0, cmds, size);
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objs[0].handle = cmd_bo;
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objs[0].relocation_count = 0;
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objs[0].relocs_ptr = 0;
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objs[0].alignment = 0;
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objs[0].offset = 0;
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objs[0].flags = 0;
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objs[0].rsvd1 = 0;
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objs[0].rsvd2 = 0;
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execbuf.buffers_ptr = (uintptr_t)objs;
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execbuf.buffer_count = 1;
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execbuf.batch_start_offset = 0;
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execbuf.batch_len = size;
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execbuf.cliprects_ptr = 0;
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execbuf.num_cliprects = 0;
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execbuf.DR1 = 0;
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execbuf.DR4 = 0;
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execbuf.flags = ring;
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i915_execbuffer2_set_context_id(execbuf, 0);
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execbuf.rsvd2 = 0;
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return __gem_execbuf(fd, &execbuf);
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}
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#define exec_batch(fd, bo, cmds, sz, ring, expected) \
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igt_assert_eq(__exec_batch(fd, bo, cmds, sz, ring), expected)
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static void exec_split_batch(int fd, uint32_t *cmds,
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int size, int ring, int expected_ret)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 objs[1];
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uint32_t cmd_bo;
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uint32_t noop[1024] = { 0 };
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const int alloc_size = 4096 * 2;
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const int actual_start_offset = 4096-sizeof(uint32_t);
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/* Allocate and fill a 2-page batch with noops */
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cmd_bo = gem_create(fd, alloc_size);
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gem_write(fd, cmd_bo, 0, noop, sizeof(noop));
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gem_write(fd, cmd_bo, 4096, noop, sizeof(noop));
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/* Write the provided commands such that the first dword
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* of the command buffer is the last dword of the first
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* page (i.e. the command is split across the two pages).
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*/
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gem_write(fd, cmd_bo, actual_start_offset, cmds, size);
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objs[0].handle = cmd_bo;
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objs[0].relocation_count = 0;
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objs[0].relocs_ptr = 0;
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objs[0].alignment = 0;
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objs[0].offset = 0;
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objs[0].flags = 0;
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objs[0].rsvd1 = 0;
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objs[0].rsvd2 = 0;
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execbuf.buffers_ptr = (uintptr_t)objs;
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execbuf.buffer_count = 1;
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/* NB: We want batch_start_offset and batch_len to point to the block
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* of the actual commands (i.e. at the last dword of the first page),
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* but have to adjust both the start offset and length to meet the
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* kernel driver's requirements on the alignment of those fields.
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*/
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execbuf.batch_start_offset = actual_start_offset & ~0x7;
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execbuf.batch_len =
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ALIGN(size + actual_start_offset - execbuf.batch_start_offset,
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0x8);
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execbuf.cliprects_ptr = 0;
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execbuf.num_cliprects = 0;
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execbuf.DR1 = 0;
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execbuf.DR4 = 0;
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execbuf.flags = ring;
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i915_execbuffer2_set_context_id(execbuf, 0);
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execbuf.rsvd2 = 0;
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igt_assert_eq(__gem_execbuf(fd, &execbuf), expected_ret);
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gem_sync(fd, cmd_bo);
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gem_close(fd, cmd_bo);
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}
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static void exec_batch_chained(int fd, uint32_t cmd_bo, uint32_t *cmds,
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int size, int patch_offset,
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uint64_t expected_value)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 objs[3];
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struct drm_i915_gem_relocation_entry reloc;
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struct drm_i915_gem_relocation_entry first_level_reloc;
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uint32_t target_bo = gem_create(fd, 4096);
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uint32_t first_level_bo = gem_create(fd, 4096);
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uint64_t actual_value = 0;
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static uint32_t first_level_cmds[] = {
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MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965,
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0,
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MI_BATCH_BUFFER_END,
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0,
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};
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if (IS_HASWELL(intel_get_drm_devid(fd)))
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first_level_cmds[0] |= MI_BATCH_NON_SECURE_HSW;
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gem_write(fd, first_level_bo, 0,
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first_level_cmds, sizeof(first_level_cmds));
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gem_write(fd, cmd_bo, 0, cmds, size);
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reloc.offset = patch_offset;
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reloc.delta = 0;
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reloc.target_handle = target_bo;
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reloc.read_domains = I915_GEM_DOMAIN_RENDER;
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reloc.write_domain = I915_GEM_DOMAIN_RENDER;
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reloc.presumed_offset = 0;
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first_level_reloc.offset = 4;
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first_level_reloc.delta = 0;
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first_level_reloc.target_handle = cmd_bo;
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first_level_reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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first_level_reloc.write_domain = 0;
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first_level_reloc.presumed_offset = 0;
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objs[0].handle = target_bo;
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objs[0].relocation_count = 0;
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objs[0].relocs_ptr = 0;
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objs[0].alignment = 0;
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objs[0].offset = 0;
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objs[0].flags = 0;
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objs[0].rsvd1 = 0;
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objs[0].rsvd2 = 0;
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objs[1].handle = cmd_bo;
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objs[1].relocation_count = 1;
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objs[1].relocs_ptr = (uintptr_t)&reloc;
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objs[1].alignment = 0;
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objs[1].offset = 0;
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objs[1].flags = 0;
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objs[1].rsvd1 = 0;
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objs[1].rsvd2 = 0;
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objs[2].handle = first_level_bo;
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objs[2].relocation_count = 1;
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objs[2].relocs_ptr = (uintptr_t)&first_level_reloc;
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objs[2].alignment = 0;
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objs[2].offset = 0;
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objs[2].flags = 0;
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objs[2].rsvd1 = 0;
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objs[2].rsvd2 = 0;
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execbuf.buffers_ptr = (uintptr_t)objs;
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execbuf.buffer_count = 3;
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execbuf.batch_start_offset = 0;
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execbuf.batch_len = sizeof(first_level_cmds);
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execbuf.cliprects_ptr = 0;
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execbuf.num_cliprects = 0;
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execbuf.DR1 = 0;
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execbuf.DR4 = 0;
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execbuf.flags = I915_EXEC_RENDER;
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i915_execbuffer2_set_context_id(execbuf, 0);
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execbuf.rsvd2 = 0;
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gem_execbuf(fd, &execbuf);
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gem_sync(fd, cmd_bo);
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gem_read(fd,target_bo, 0, &actual_value, sizeof(actual_value));
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igt_assert_eq(expected_value, actual_value);
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gem_close(fd, first_level_bo);
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gem_close(fd, target_bo);
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}
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uint32_t handle;
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int fd;
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#define MI_ARB_ON_OFF (0x8 << 23)
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#define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
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#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
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#define PIPE_CONTROL_QW_WRITE (1<<14)
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#define PIPE_CONTROL_LRI_POST_OP (1<<23)
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#define OACONTROL 0x2360
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igt_main
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{
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igt_fixture {
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int parser_version = 0;
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drm_i915_getparam_t gp;
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int rc;
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fd = drm_open_driver(DRIVER_INTEL);
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gp.param = I915_PARAM_CMD_PARSER_VERSION;
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gp.value = &parser_version;
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rc = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
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igt_require(!rc && parser_version > 0);
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igt_require(gem_uses_aliasing_ppgtt(fd));
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handle = gem_create(fd, 4096);
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/* ATM cmd parser only exists on gen7. */
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igt_require(intel_gen(intel_get_drm_devid(fd)) == 7);
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}
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igt_subtest("basic-allowed") {
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uint32_t pc[] = {
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GFX_OP_PIPE_CONTROL,
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PIPE_CONTROL_QW_WRITE,
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0, /* To be patched */
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0x12000000,
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0,
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MI_BATCH_BUFFER_END,
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};
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exec_batch_patched(fd, handle,
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pc, sizeof(pc),
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8, /* patch offset, */
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0x12000000);
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}
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igt_subtest("basic-rejected") {
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uint32_t arb_on_off[] = {
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MI_ARB_ON_OFF,
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MI_BATCH_BUFFER_END,
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};
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uint32_t display_flip[] = {
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MI_DISPLAY_FLIP,
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0, 0, 0,
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MI_BATCH_BUFFER_END,
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0
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};
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exec_batch(fd, handle,
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arb_on_off, sizeof(arb_on_off),
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I915_EXEC_RENDER,
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-EINVAL);
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exec_batch(fd, handle,
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arb_on_off, sizeof(arb_on_off),
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I915_EXEC_BSD,
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-EINVAL);
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if (gem_has_vebox(fd)) {
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exec_batch(fd, handle,
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arb_on_off, sizeof(arb_on_off),
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I915_EXEC_VEBOX,
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-EINVAL);
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}
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exec_batch(fd, handle,
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display_flip, sizeof(display_flip),
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I915_EXEC_BLT,
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-EINVAL);
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}
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igt_subtest("registers") {
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uint32_t lri_bad[] = {
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MI_LOAD_REGISTER_IMM,
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0, /* disallowed register address */
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0x12000000,
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MI_BATCH_BUFFER_END,
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};
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uint32_t lri_ok[] = {
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MI_LOAD_REGISTER_IMM,
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0x5280, /* allowed register address (SO_WRITE_OFFSET[0]) */
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0x1,
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MI_BATCH_BUFFER_END,
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};
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exec_batch(fd, handle,
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lri_bad, sizeof(lri_bad),
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I915_EXEC_RENDER,
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-EINVAL);
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exec_batch(fd, handle,
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lri_ok, sizeof(lri_ok),
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I915_EXEC_RENDER,
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0);
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}
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igt_subtest("bitmasks") {
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uint32_t pc[] = {
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GFX_OP_PIPE_CONTROL,
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(PIPE_CONTROL_QW_WRITE |
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PIPE_CONTROL_LRI_POST_OP),
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0, /* To be patched */
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0x12000000,
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0,
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MI_BATCH_BUFFER_END,
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};
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exec_batch(fd, handle,
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pc, sizeof(pc),
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I915_EXEC_RENDER,
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-EINVAL);
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}
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igt_subtest("batch-without-end") {
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uint32_t noop[1024] = { 0 };
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exec_batch(fd, handle,
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noop, sizeof(noop),
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I915_EXEC_RENDER,
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-EINVAL);
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}
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igt_subtest("cmd-crossing-page") {
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uint32_t lri_ok[] = {
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MI_LOAD_REGISTER_IMM,
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0x5280, /* allowed register address (SO_WRITE_OFFSET[0]) */
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0x1,
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MI_BATCH_BUFFER_END,
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};
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exec_split_batch(fd,
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lri_ok, sizeof(lri_ok),
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I915_EXEC_RENDER,
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0);
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}
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igt_subtest("oacontrol-tracking") {
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uint32_t lri_ok[] = {
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MI_LOAD_REGISTER_IMM,
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OACONTROL,
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0x31337000,
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MI_LOAD_REGISTER_IMM,
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OACONTROL,
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0x0,
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MI_BATCH_BUFFER_END,
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0
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};
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uint32_t lri_bad[] = {
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MI_LOAD_REGISTER_IMM,
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OACONTROL,
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0x31337000,
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MI_BATCH_BUFFER_END,
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};
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uint32_t lri_extra_bad[] = {
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MI_LOAD_REGISTER_IMM,
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OACONTROL,
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0x31337000,
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MI_LOAD_REGISTER_IMM,
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OACONTROL,
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0x0,
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MI_LOAD_REGISTER_IMM,
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OACONTROL,
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0x31337000,
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MI_BATCH_BUFFER_END,
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};
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exec_batch(fd, handle,
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lri_ok, sizeof(lri_ok),
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I915_EXEC_RENDER,
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0);
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exec_batch(fd, handle,
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lri_bad, sizeof(lri_bad),
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I915_EXEC_RENDER,
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-EINVAL);
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exec_batch(fd, handle,
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lri_extra_bad, sizeof(lri_extra_bad),
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I915_EXEC_RENDER,
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-EINVAL);
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}
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igt_subtest("chained-batch") {
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uint32_t pc[] = {
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GFX_OP_PIPE_CONTROL,
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PIPE_CONTROL_QW_WRITE,
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0, /* To be patched */
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0x12000000,
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0,
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MI_BATCH_BUFFER_END,
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|
};
|
|
exec_batch_chained(fd, handle,
|
|
pc, sizeof(pc),
|
|
8, /* patch offset, */
|
|
0x12000000);
|
|
}
|
|
|
|
igt_fixture {
|
|
gem_close(fd, handle);
|
|
|
|
close(fd);
|
|
}
|
|
}
|