mirror of
				https://github.com/tiagovignatti/intel-gpu-tools.git
				synced 2025-11-04 12:07:12 +00:00 
			
		
		
		
	Apply the new API to all call sites within the test suite using the following semantic patch: // Semantic patch for replacing drm_open_any* with arch-specific drm_open_driver* calls @@ identifier i =~ "\bdrm_open_any\b"; @@ - i() + drm_open_driver(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_master\b"; @@ - i() + drm_open_driver_master(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_render\b"; @@ - i() + drm_open_driver_render(DRIVER_INTEL) @@ identifier i =~ "\b__drm_open_any\b"; @@ - i() + __drm_open_driver(DRIVER_INTEL) Signed-off-by: Micah Fedke <micah.fedke@collabora.co.uk> Signed-off-by: Thomas Wood <thomas.wood@intel.com>
		
			
				
	
	
		
			194 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			194 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright © 2015 Intel Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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 * IN THE SOFTWARE.
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 *
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 */
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/*
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 * Testcase: Test that only specific ioctl report a wedged GPU.
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 *
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 */
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#include "igt.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/ioctl.h>
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#include <drm.h>
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IGT_TEST_DESCRIPTION("Test that specific ioctls report a wedged GPU (EIO).");
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static bool i915_reset_control(bool enable)
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{
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	const char *path = "/sys/module/i915/parameters/reset";
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	int fd, ret;
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	igt_debug("%s GPU reset\n", enable ? "Enabling" : "Disabling");
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	fd = open(path, O_RDWR);
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	igt_require(fd >= 0);
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	ret = write(fd, &"NY"[enable], 1) == 1;
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	close(fd);
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	return ret;
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}
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static bool i915_wedged_set(void)
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{
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	int fd, ret;
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	igt_debug("Triggering GPU reset\n");
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	fd = igt_debugfs_open("i915_wedged", O_RDWR);
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	igt_require(fd >= 0);
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	ret = write(fd, "1\n", 2) == 2;
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	close(fd);
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	return ret;
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}
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static void trigger_reset(int fd)
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{
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	igt_assert(i915_wedged_set());
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	/* And just check the gpu is indeed running again */
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	igt_debug("Checking that the GPU recovered\n");
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	gem_quiescent_gpu(fd);
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}
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static void wedge_gpu(int fd)
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{
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	/* First idle the GPU then disable GPU resets before injecting a hang */
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	gem_quiescent_gpu(fd);
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	igt_require(i915_reset_control(false));
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	igt_debug("Wedging GPU by injecting hang\n");
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	igt_post_hang_ring(fd, igt_hang_ring(fd, I915_EXEC_DEFAULT));
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	igt_assert(i915_reset_control(true));
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}
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static int __gem_throttle(int fd)
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{
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	int err = 0;
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	if (drmIoctl(fd, DRM_IOCTL_I915_GEM_THROTTLE, NULL))
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		err = -errno;
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	return err;
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}
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static void test_throttle(int fd)
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{
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	wedge_gpu(fd);
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	igt_assert_eq(__gem_throttle(fd), -EIO);
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	trigger_reset(fd);
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}
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static int __gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb)
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{
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	int err = 0;
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	if (drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, eb))
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		err = -errno;
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	return err;
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}
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static void test_execbuf(int fd)
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{
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	struct drm_i915_gem_execbuffer2 execbuf;
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	struct drm_i915_gem_exec_object2 exec;
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	uint32_t tmp[] = { MI_BATCH_BUFFER_END };
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	memset(&exec, 0, sizeof(exec));
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	memset(&execbuf, 0, sizeof(execbuf));
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	exec.handle = gem_create(fd, 4096);
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	gem_write(fd, exec.handle, 0, tmp, sizeof(tmp));
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	execbuf.buffers_ptr = (uintptr_t)&exec;
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	execbuf.buffer_count = 1;
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	wedge_gpu(fd);
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	igt_assert_eq(__gem_execbuf(fd, &execbuf), -EIO);
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	gem_close(fd, exec.handle);
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	trigger_reset(fd);
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}
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static int __gem_wait(int fd, uint32_t handle, int64_t timeout)
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{
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	struct drm_i915_gem_wait wait;
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	int err = 0;
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	memset(&wait, 0, sizeof(wait));
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	wait.bo_handle = handle;
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	wait.timeout_ns = timeout;
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	if (drmIoctl(fd, DRM_IOCTL_I915_GEM_WAIT, &wait))
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		err = -errno;
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	return err;
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}
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static void test_wait(int fd)
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{
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	igt_hang_ring_t hang;
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	hang = igt_hang_ring(fd, I915_EXEC_DEFAULT);
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	igt_assert_eq(__gem_wait(fd, hang.handle, -1), -EIO);
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	igt_post_hang_ring(fd, hang);
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	trigger_reset(fd);
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}
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igt_main
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{
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	int fd = -1;
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	igt_skip_on_simulation();
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	igt_fixture {
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		fd = drm_open_driver(DRIVER_INTEL);
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		igt_require_hang_ring(fd, -1);
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	}
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	igt_subtest("throttle")
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		test_throttle(fd);
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	igt_subtest("execbuf")
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		test_execbuf(fd);
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	igt_subtest("wait")
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		test_wait(fd);
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	igt_fixture
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		close(fd);
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}
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