mirror of
				https://github.com/tiagovignatti/intel-gpu-tools.git
				synced 2025-11-04 12:07:12 +00:00 
			
		
		
		
	Apply the new API to all call sites within the test suite using the following semantic patch: // Semantic patch for replacing drm_open_any* with arch-specific drm_open_driver* calls @@ identifier i =~ "\bdrm_open_any\b"; @@ - i() + drm_open_driver(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_master\b"; @@ - i() + drm_open_driver_master(DRIVER_INTEL) @@ identifier i =~ "\bdrm_open_any_render\b"; @@ - i() + drm_open_driver_render(DRIVER_INTEL) @@ identifier i =~ "\b__drm_open_any\b"; @@ - i() + __drm_open_driver(DRIVER_INTEL) Signed-off-by: Micah Fedke <micah.fedke@collabora.co.uk> Signed-off-by: Thomas Wood <thomas.wood@intel.com>
		
			
				
	
	
		
			149 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			149 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright © 2011 Intel Corporation
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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 * IN THE SOFTWARE.
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 *
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 * Authors:
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 *    Daniel Vetter <daniel.vetter@ffwll.ch>
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 *
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 */
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/*
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 * Testcase: Test the CS prefetch behaviour on batches
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 *
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 * Historically the batch prefetcher doesn't check whether it's crossing page
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 * boundaries and likes to throw up when it gets a pagefault in return for his
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 * over-eager behaviour. Check for this.
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 *
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 * This test for a bug where we've failed to plug a scratch pte entry into the
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 * very last gtt pte.
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 */
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#include "igt.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include <drm.h>
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#include "intel_bufmgr.h"
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IGT_TEST_DESCRIPTION("Test the CS prefetch behaviour on batches.");
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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static void exec(int fd, uint32_t handle)
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{
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	struct drm_i915_gem_execbuffer2 execbuf;
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	struct drm_i915_gem_exec_object2 gem_exec[1];
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	memset(gem_exec, 0, sizeof(gem_exec));
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	gem_exec[0].handle = handle;
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	memset(&execbuf, 0, sizeof(execbuf));
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	execbuf.buffers_ptr = (uintptr_t)gem_exec;
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	execbuf.buffer_count = 1;
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	execbuf.batch_start_offset = 0;
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	execbuf.batch_len = 4096;
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	gem_execbuf(fd, &execbuf);
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	gem_sync(fd, handle);
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}
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igt_simple_main
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{
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	uint32_t batch_end[4] = {MI_BATCH_BUFFER_END, 0, 0, 0};
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	int fd, i, ret;
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	uint64_t aper_size;
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	int count;
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	drm_intel_bo *sample_batch_bo;
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	igt_skip_on_simulation();
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	fd = drm_open_driver(DRIVER_INTEL);
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	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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	igt_assert(bufmgr);
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	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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	aper_size = gem_aperture_size(fd);
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	/* presume a big per-bo overhead */
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	igt_skip_on_f(intel_get_total_ram_mb() < (aper_size / (1024*1024)) * 3 / 2,
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		      "not enough mem to run test\n");
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	count = aper_size / 4096;
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	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
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	igt_assert(batch);
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	sample_batch_bo = drm_intel_bo_alloc(bufmgr, "", 4096, 4096);
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	igt_assert(sample_batch_bo);
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	ret = drm_intel_bo_subdata(sample_batch_bo, 4096-sizeof(batch_end),
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				   sizeof(batch_end), batch_end);
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	igt_assert(ret == 0);
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	/* fill the entire gart with batches and run them */
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	for (i = 0; i < count; i++) {
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		drm_intel_bo *batch_bo;
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		batch_bo = drm_intel_bo_alloc(bufmgr, "", 4096, 4096);
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		igt_assert(batch_bo);
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		/* copy the sample batch with the gpu to the new one, so that we
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		 * also test the unmappable part of the gtt. */
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		BLIT_COPY_BATCH_START(0);
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		OUT_BATCH((3 << 24) | /* 32 bits */
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			  (0xcc << 16) | /* copy ROP */
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			  4096);
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		OUT_BATCH(0); /* dst y1,x1 */
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		OUT_BATCH((1 << 16) | 1024);
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		OUT_RELOC_FENCED(batch_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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		OUT_BATCH((0 << 16) | 0); /* src x1, y1 */
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		OUT_BATCH(4096);
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		OUT_RELOC_FENCED(sample_batch_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
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		ADVANCE_BATCH();
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		intel_batchbuffer_flush(batch);
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		if (i % 100 == 0)
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			gem_sync(fd, batch_bo->handle);
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		drm_intel_bo_disable_reuse(batch_bo);
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		/* launch the newly created batch */
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		exec(fd, batch_bo->handle);
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		// leak buffers
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		//drm_intel_bo_unreference(batch_bo);
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		igt_progress("gem_cs_prefetch: ", i, count);
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	}
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	igt_info("Test suceeded, cleanup up - this might take a while.\n");
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	drm_intel_bufmgr_destroy(bufmgr);
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	close(fd);
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}
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