mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
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4bc68b1baa
Add the Kabylake GT4 PCI IDs as defined in this kernel patch.
commit 8b10c0cf21ec84618d4bf02c73c0543500ece68d
Author: Deepak S <deepak.s@intel.com>
Date: Wed Oct 28 12:21:12 2015 -0700
drm/i915/kbl: Add Kabylake GT4 PCI ID
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
521 lines
19 KiB
C
521 lines
19 KiB
C
/*
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* Copyright © 2007 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifndef _INTEL_CHIPSET_H
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#define _INTEL_CHIPSET_H
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#include <pciaccess.h>
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struct pci_device *intel_get_pci_device(void);
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uint32_t intel_get_drm_devid(int fd);
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int intel_gen(uint32_t devid);
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extern enum pch_type intel_pch;
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enum pch_type {
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PCH_NONE,
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PCH_IBX,
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PCH_CPT,
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PCH_LPT,
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};
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void intel_check_pch(void);
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#define HAS_IBX (intel_pch == PCH_IBX)
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#define HAS_CPT (intel_pch == PCH_CPT)
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#define HAS_LPT (intel_pch == PCH_LPT)
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/* Exclude chipset #defines, they just add noise */
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#ifndef __GTK_DOC_IGNORE__
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#define PCI_CHIP_I810 0x7121
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#define PCI_CHIP_I810_DC100 0x7123
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#define PCI_CHIP_I810_E 0x7125
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#define PCI_CHIP_I815 0x1132
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#define PCI_CHIP_I830_M 0x3577
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#define PCI_CHIP_845_G 0x2562
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#define PCI_CHIP_I854_G 0x358e
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#define PCI_CHIP_I855_GM 0x3582
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#define PCI_CHIP_I865_G 0x2572
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#define PCI_CHIP_I915_G 0x2582
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#define PCI_CHIP_E7221_G 0x258A
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#define PCI_CHIP_I915_GM 0x2592
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#define PCI_CHIP_I945_G 0x2772
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#define PCI_CHIP_I945_GM 0x27A2
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#define PCI_CHIP_I945_GME 0x27AE
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#define PCI_CHIP_Q35_G 0x29B2
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#define PCI_CHIP_G33_G 0x29C2
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#define PCI_CHIP_Q33_G 0x29D2
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#define PCI_CHIP_IGD_GM 0xA011
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#define PCI_CHIP_IGD_G 0xA001
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#define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
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#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
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#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
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#define PCI_CHIP_I965_G 0x29A2
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#define PCI_CHIP_I965_Q 0x2992
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#define PCI_CHIP_I965_G_1 0x2982
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#define PCI_CHIP_I946_GZ 0x2972
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#define PCI_CHIP_I965_GM 0x2A02
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#define PCI_CHIP_I965_GME 0x2A12
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#define PCI_CHIP_GM45_GM 0x2A42
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#define PCI_CHIP_IGD_E_G 0x2E02
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#define PCI_CHIP_Q45_G 0x2E12
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#define PCI_CHIP_G45_G 0x2E22
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#define PCI_CHIP_G41_G 0x2E32
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#define PCI_CHIP_ILD_G 0x0042
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#define PCI_CHIP_ILM_G 0x0046
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#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
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#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
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#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
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#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
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#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
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#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
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#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
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#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
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#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
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#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
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#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
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#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
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#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
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#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
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#define PCI_CHIP_HASWELL_GT2 0x0412
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#define PCI_CHIP_HASWELL_GT3 0x0422
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#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
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#define PCI_CHIP_HASWELL_M_GT2 0x0416
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#define PCI_CHIP_HASWELL_M_GT3 0x0426
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#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
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#define PCI_CHIP_HASWELL_S_GT2 0x041A
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#define PCI_CHIP_HASWELL_S_GT3 0x042A
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#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
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#define PCI_CHIP_HASWELL_B_GT2 0x041B
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#define PCI_CHIP_HASWELL_B_GT3 0x042B
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#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
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#define PCI_CHIP_HASWELL_E_GT2 0x041E
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#define PCI_CHIP_HASWELL_E_GT3 0x042E
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#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
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#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
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#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
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#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
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#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
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#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
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#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
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#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
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#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
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#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
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#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
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#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
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#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
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#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
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#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
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#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
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#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
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#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
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#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
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#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
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#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
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#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
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#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
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#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
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#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
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#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
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#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
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#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
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#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
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#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
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#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
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#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
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#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
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#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
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#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
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#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
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#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
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#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
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#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
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#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
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#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
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#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
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#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
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#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
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#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
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#define BDW_SPARE 0x2
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#define BDW_ULT 0x6
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#define BDW_HALO 0xb
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#define BDW_SERVER 0xa
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#define BDW_WORKSTATION 0xd
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#define BDW_ULX 0xe
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#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
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#define PCI_CHIP_VALLEYVIEW_1 0x0f31
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#define PCI_CHIP_VALLEYVIEW_2 0x0f32
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#define PCI_CHIP_VALLEYVIEW_3 0x0f33
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#define PCI_CHIP_CHERRYVIEW_0 0x22b0
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#define PCI_CHIP_CHERRYVIEW_1 0x22b1
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#define PCI_CHIP_CHERRYVIEW_2 0x22b2
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#define PCI_CHIP_CHERRYVIEW_3 0x22b3
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#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
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#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
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#define PCI_CHIP_SKYLAKE_ULT_GT3 0x1926
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#define PCI_CHIP_SKYLAKE_ULT_GT2F 0x1921
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#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E
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#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
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#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
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#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
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#define PCI_CHIP_SKYLAKE_DT_GT4 0x1932
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#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
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#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B
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#define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B
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#define PCI_CHIP_SKYLAKE_HALO_GT4 0x193B
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#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A
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#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A
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#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
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#define PCI_CHIP_SKYLAKE_SRV_GT4 0x193A
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#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
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#define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D
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#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916
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#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913
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#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906
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#define PCI_CHIP_KABYLAKE_ULT_GT3 0x5926
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#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921
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#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
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#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
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#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E
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#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
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#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917
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#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
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#define PCI_CHIP_KABYLAKE_DT_GT4 0x5932
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#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B
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#define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B
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#define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B
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#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B
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#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A
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#define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A
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#define PCI_CHIP_KABYLAKE_SRV_GT4 0x593A
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#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
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#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
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#define PCI_CHIP_KABYLAKE_WKS_GT4 0x593D
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#define PCI_CHIP_BROXTON_0 0x0A84
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#define PCI_CHIP_BROXTON_1 0x1A84
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#define PCI_CHIP_BROXTON_2 0x5A84
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#endif /* __GTK_DOC_IGNORE__ */
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#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
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(devid) == PCI_CHIP_I915_GM || \
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(devid) == PCI_CHIP_I945_GM || \
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(devid) == PCI_CHIP_I945_GME || \
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(devid) == PCI_CHIP_I965_GM || \
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(devid) == PCI_CHIP_I965_GME || \
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(devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
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(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
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(devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
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#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
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(devid) == PCI_CHIP_Q45_G || \
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(devid) == PCI_CHIP_G45_G || \
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(devid) == PCI_CHIP_G41_G)
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#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
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#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
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#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
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#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
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#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
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(devid) == PCI_CHIP_E7221_G || \
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(devid) == PCI_CHIP_I915_GM)
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#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
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(devid) == PCI_CHIP_I945_GME)
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#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
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(devid) == PCI_CHIP_I945_GM || \
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(devid) == PCI_CHIP_I945_GME || \
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IS_G33(devid))
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#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
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(devid) == PCI_CHIP_Q33_G || \
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(devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
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#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
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(devid) == PCI_CHIP_845_G || \
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(devid) == PCI_CHIP_I854_G || \
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(devid) == PCI_CHIP_I855_GM || \
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(devid) == PCI_CHIP_I865_G)
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#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
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#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
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(devid) == PCI_CHIP_I965_Q || \
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(devid) == PCI_CHIP_I965_G_1 || \
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(devid) == PCI_CHIP_I965_GM || \
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(devid) == PCI_CHIP_I965_GME || \
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(devid) == PCI_CHIP_I946_GZ || \
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IS_G4X(devid))
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#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
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#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
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(devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
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(devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
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(devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
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(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
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(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
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(devid) == PCI_CHIP_SANDYBRIDGE_S)
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#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
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IS_HASWELL(devid) || \
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IS_VALLEYVIEW(devid))
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#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
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(devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
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(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
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(devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
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(devid) == PCI_CHIP_IVYBRIDGE_S || \
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(devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
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#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
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(devid) == PCI_CHIP_VALLEYVIEW_1 || \
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(devid) == PCI_CHIP_VALLEYVIEW_2 || \
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(devid) == PCI_CHIP_VALLEYVIEW_3)
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#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
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(devid) == PCI_CHIP_HASWELL_M_GT1 || \
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(devid) == PCI_CHIP_HASWELL_S_GT1 || \
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(devid) == PCI_CHIP_HASWELL_B_GT1 || \
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(devid) == PCI_CHIP_HASWELL_E_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
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#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
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(devid) == PCI_CHIP_HASWELL_M_GT2 || \
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(devid) == PCI_CHIP_HASWELL_S_GT2 || \
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(devid) == PCI_CHIP_HASWELL_B_GT2 || \
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(devid) == PCI_CHIP_HASWELL_E_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
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#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
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(devid) == PCI_CHIP_HASWELL_M_GT3 || \
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(devid) == PCI_CHIP_HASWELL_S_GT3 || \
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(devid) == PCI_CHIP_HASWELL_B_GT3 || \
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(devid) == PCI_CHIP_HASWELL_E_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
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#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
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IS_HSW_GT2(devid) || \
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IS_HSW_GT3(devid))
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#define IS_BROADWELL(devid) ((((devid) & 0xff00) != 0x1600) ? 0 : \
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((((devid) & 0x00f0) >> 4) > 3) ? 0 : \
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(((devid) & 0x000f) == BDW_SPARE) ? 1 : \
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(((devid) & 0x000f) == BDW_ULT) ? 1 : \
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(((devid) & 0x000f) == BDW_HALO) ? 1 : \
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(((devid) & 0x000f) == BDW_SERVER) ? 1 : \
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(((devid) & 0x000f) == BDW_WORKSTATION) ? 1 : \
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(((devid) & 0x000f) == BDW_ULX) ? 1 : 0)
|
|
|
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#define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \
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(devid) == PCI_CHIP_CHERRYVIEW_1 || \
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(devid) == PCI_CHIP_CHERRYVIEW_2 || \
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(devid) == PCI_CHIP_CHERRYVIEW_3)
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|
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#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
|
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IS_CHERRYVIEW(devid))
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#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
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(devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
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|
(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
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|
(devid) == PCI_CHIP_SKYLAKE_HALO_GT1 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
|
|
|
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#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
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|
(devid) == PCI_CHIP_SKYLAKE_ULT_GT2F || \
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|
(devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
|
|
|
|
#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
|
|
|
|
#define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_HALO_GT4 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_WKS_GT4 || \
|
|
(devid) == PCI_CHIP_SKYLAKE_SRV_GT4)
|
|
|
|
#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_DT_GT1_5|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_ULT_GT1|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_ULX_GT1|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_HALO_GT1|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
|
|
|
|
#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_ULT_GT2F|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_ULX_GT2|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_HALO_GT2|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_SRV_GT2|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
|
|
|
|
#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_HALO_GT3|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_SRV_GT3)
|
|
|
|
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT4|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_HALO_GT4|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_SRV_GT4|| \
|
|
(devid) == PCI_CHIP_KABYLAKE_WKS_GT4)
|
|
|
|
#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \
|
|
IS_KBL_GT2(devid) || \
|
|
IS_KBL_GT3(devid) || \
|
|
IS_KBL_GT4(devid))
|
|
|
|
#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
|
|
IS_SKL_GT2(devid) || \
|
|
IS_SKL_GT3(devid) || \
|
|
IS_SKL_GT4(devid))
|
|
|
|
#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
|
|
(devid) == PCI_CHIP_BROXTON_1 || \
|
|
(devid) == PCI_CHIP_BROXTON_2)
|
|
|
|
#define IS_GEN9(devid) (IS_KABYLAKE(devid) || \
|
|
IS_SKYLAKE(devid) || \
|
|
IS_BROXTON(devid))
|
|
|
|
#define IS_965(devid) (IS_GEN4(devid) || \
|
|
IS_GEN5(devid) || \
|
|
IS_GEN6(devid) || \
|
|
IS_GEN7(devid) || \
|
|
IS_GEN8(devid) || \
|
|
IS_GEN9(devid))
|
|
|
|
#define IS_9XX(devid) (IS_GEN3(devid) || \
|
|
IS_GEN4(devid) || \
|
|
IS_GEN5(devid) || \
|
|
IS_GEN6(devid) || \
|
|
IS_GEN7(devid) || \
|
|
IS_GEN8(devid) || \
|
|
IS_GEN9(devid))
|
|
|
|
#define IS_INTEL(devid) (IS_GEN2(devid) || \
|
|
IS_GEN3(devid) || \
|
|
IS_GEN4(devid) || \
|
|
IS_GEN5(devid) || \
|
|
IS_GEN6(devid) || \
|
|
IS_GEN7(devid) || \
|
|
IS_GEN8(devid) || \
|
|
IS_GEN9(devid))
|
|
|
|
#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
|
|
IS_GEN6(devid) || \
|
|
IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
|
|
IS_BROADWELL(devid) || \
|
|
IS_SKYLAKE(devid))
|
|
|
|
#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
|
|
IS_GEN7(devid) || \
|
|
IS_GEN8(devid) || \
|
|
IS_GEN9(devid))
|
|
|
|
#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \
|
|
IS_GEN6(devid) || \
|
|
IS_GEN7(devid) || \
|
|
IS_GEN8(devid) || \
|
|
IS_GEN9(devid))
|
|
|
|
#define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
|
|
(devid) == PCI_CHIP_I965_G_1 || \
|
|
(devid) == PCI_CHIP_I965_Q || \
|
|
(devid) == PCI_CHIP_I965_G)
|
|
|
|
#define IS_CRESTLINE(devid) ((devid) == PCI_CHIP_I965_GM || \
|
|
(devid) == PCI_CHIP_I965_GME)
|
|
|
|
#define HAS_VEBOX_RING(devid) (IS_HASWELL(devid))
|
|
|
|
#endif /* _INTEL_CHIPSET_H */
|