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https://github.com/tiagovignatti/intel-gpu-tools.git
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62873796c4
high level summary of the files:
* debug_rdata - get current state from debug registers. Helpful
when developing the debugger, and could serve some purpose in the
future.
* eudb - the debugger itself
* eviction_macro - generate the proper macro to flush the EU render
cache until I get control flow working
* pre_cpp - an evaluating c preprocesser like thing, to be used before
cpp
* sr - the system routine, exception handler which runs on the EU
* test - a very basic test system routine
* debug.h
278 lines
8.3 KiB
Plaintext
278 lines
8.3 KiB
Plaintext
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Ben Widawsky <ben@bwidawsk.net>
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*
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*/
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#include "debug.h"
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#include "evict.h"
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#define CR0_0_ME_STATE_CTRL (1 << 31)
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#define CR0_0_BP_SUPPRESS (1 << 15)
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#define CR0_0_SPF_EN (1 << 2)
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#define CR0_0_ACC_DIS (1 << 1)
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#define CR0_1_BES_CTRL (1 << 31)
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#define CR0_1_HALT_CTRL (1 << 30)
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#define CR0_1_SOFT_EXCEPTION_CTRL (1 << 29)
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#define CR0_1_ILLGL_OP_STS (1 << 28)
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#define CR0_1_STACK_OVRFLW_STS (1 << 27)
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#define CR0_0_ENTRY_UNMASK (CR0_0_SPF_EN | CR0_0_ACC_DIS)
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// TODO: Need to fix this for non breakpoint case
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#define CR0_1_ENTRY_UNMASK ~(CR0_1_BES_CTRL)
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#define CR0_0_RETURN_MASK ~(CR0_0_ME_STATE_CTRL | CR0_0_SPF_EN | CR0_0_ACC_DIS)
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// TODO: not sure how to make this not hardcoded
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#define PER_THREAD_SCRATCH_SIZE (1 << 20)
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#define PER_THREAD_QWORDS (PER_THREAD_SCRATCH_SIZE >> 4)
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/* Should get this from brw_defines.h */
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#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
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#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
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#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
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#define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
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#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
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/* desc field, ie. dword3 6.3.66.2 and 2.11.2.1.4 */
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#define SEND_MLEN_5 (5<<25)
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#define SEND_MLEN_3 (3<<25)
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#define SEND_MLEN_2 (2<<25)
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#define SEND_MLEN_1 (1<<25)
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#define SEND_RLEN_1 (1<<20)
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#define SEND_RLEN_0 (0<<20)
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#define SEND_HEADER_PRESENT (1<<19)
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#define SEND_WRITE_COMMIT (1<<17)
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#define SEND_TYPE_WRITE (GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE<<13)
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#define SEND_TYPE_READ (BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ<<13)
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#define SEND_BLOCK_SIZE1 (BRW_DATAPORT_OWORD_BLOCK_2_OWORDS<<8)
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#define SEND_BLOCK_SIZE2 (BRW_DATAPORT_OWORD_BLOCK_4_OWORDS<<8)
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#define SEND_BLOCK_SIZE4 (BRW_DATAPORT_OWORD_BLOCK_8_OWORDS<<8)
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#define SEND_BINDING_TABLE (255<<0)
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// No write commit
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#define WRITE_DESC1_XXX SEND_BINDING_TABLE | SEND_BLOCK_SIZE1 | SEND_TYPE_WRITE | SEND_HEADER_PRESENT | SEND_MLEN_2
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#define WRITE_DESC1_WC SEND_BINDING_TABLE | SEND_BLOCK_SIZE1 | SEND_TYPE_WRITE | SEND_HEADER_PRESENT | SEND_MLEN_2 | SEND_WRITE_COMMIT
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#define WRITE_DESC2 SEND_BINDING_TABLE | SEND_BLOCK_SIZE2 | SEND_TYPE_WRITE | SEND_HEADER_PRESENT | SEND_MLEN_3
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#define WRITE_DESC4 SEND_BINDING_TABLE | SEND_BLOCK_SIZE4 | SEND_TYPE_WRITE | SEND_HEADER_PRESENT | SEND_MLEN_5
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#define RECV_DESC1 SEND_BINDING_TABLE | SEND_BLOCK_SIZE1 | SEND_TYPE_READ | SEND_HEADER_PRESENT | SEND_MLEN_1 | SEND_RLEN_1
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//#define SEND_DESC1 0x40902FF
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#define SEND_DESC1_WC 0x40b02FF
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/* ex_desc field 6.3.66.2 */
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#define SEND_DP_RENDER_CACHE (5<<0)
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#define SEND_EOT (1<<5)
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#define SEND_EX_DESC SEND_DP_RENDER_CACHE
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/**
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* WRITE_SCRATCH1 - Write 2 owords.
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* cdst.2 - offset
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* cdst.5 - per thread scratch base, relative to gsba??
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* cdst+1 - data to be written.
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*/
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#define WRITE_SCRATCH1(cdst) \
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send (16) null cdst SEND_EX_DESC WRITE_DESC1_XXX FLAGS
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#define WRITE_SCRATCH1_WC(cdst) \
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send (16) g1 cdst SEND_EX_DESC WRITE_DESC1_WC FLAGS
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#define WRITE_SCRATCH2(cdst) \
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send (16) null cdst SEND_EX_DESC WRITE_DESC2 FLAGS
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#define WRITE_SCRATCH4(cdst) \
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send (16) null cdst SEND_EX_DESC WRITE_DESC4 FLAGS
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/**
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* READ_SCRATCH1 - Read 2 owords.
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* cdst.2 - offset
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* cdst.5 - per thread scratch base, relative to gsba??
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* grf - register where read data is populated.
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*/
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#define READ_SCRATCH1(grf, cdst) \
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send (16) grf:ud cdst SEND_EX_DESC RECV_DESC1 FLAGS
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/**
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* SET_OFFSET - setup mrf for the given offset prior to a send instruction.
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* mrf - message register to be used as the header.
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* offset - offset.
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*
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* If a WRITE_SCRATCH follows, mrf+1 -> mrf+1+n should contain the data to be
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* written.
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*/
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#define SET_OFFSET(mrf, offset) \
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mov (1) mrf.5:ud g0.5:ud FLAGS; \
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mov (1) mrf.2:ud offset:ud FLAGS
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/**
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* SAVE_CRF - save the control register
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* clobbers: m0.2, m0.5
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*/
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#define CR_OFFSET 0x40
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#define SAVE_CRF \
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SET_OFFSET(m0, CR_OFFSET); \
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mov (8) m1:ud 0xdeadbeef:ud FLAGS; \
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mov (1) m1.0:ud cr0.0 FLAGS; \
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mov (1) m1.1:ud cr0.1 FLAGS; \
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mov (1) m1.2:ud cr0.2 FLAGS; \
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mov (1) m1.3:ud sr0:ud FLAGS; \
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WRITE_SCRATCH1(m0)
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/*
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* clobbers: m0.2, m0.5
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*/
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#define STORE_GRF(grf, offset) \
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SET_OFFSET(m0, offset); \
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mov (8) m1:ud grf:ud FLAGS; \
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WRITE_SCRATCH1(m0)
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/*
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* clobbers: m0.2, m0.5
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*/
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#define LOAD_GRF(grf, offset) \
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SET_OFFSET(m0, offset); \
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READ_SCRATCH1(grf, m0)
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/*
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* clobbers: mrf.2 mrf.5
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*/
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#define STORE_MRF(mrf, offset) \
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SET_OFFSET(mrf, offset); \
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WRITE_SCRATCH1(mrf)
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/*
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* non-quirky semantics, unlike STORE_MRF
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* clobbers: g1
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*/
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#define LOAD_MRF(mrf, offset) \
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LOAD_GRF(g1, offset); \
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mov (8) mrf:ud g1:ud FLAGS
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#define SAVE_ALL_MRF \
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/* m1 is saved already */ \
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STORE_MRF(m1, 0x2); \
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STORE_MRF(m2, 0x4); \
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STORE_MRF(m3, 0x6); \
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STORE_MRF(m4, 0x8); \
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STORE_MRF(m5, 0xa); \
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STORE_MRF(m6, 0xc); \
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STORE_MRF(m7, 0xe); \
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STORE_MRF(m8, 0x10); \
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STORE_MRF(m9, 0x12); \
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STORE_MRF(m10, 0x14); \
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STORE_MRF(m11, 0x16); \
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STORE_MRF(m12, 0x18); \
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STORE_MRF(m13, 0x1a); \
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STORE_MRF(m14, 0x1c)
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#define RESTORE_ALL_MRF \
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LOAD_MRF(m15, 0x1c); \
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LOAD_MRF(m14, 0x1a); \
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LOAD_MRF(m13, 0x18); \
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LOAD_MRF(m12, 0x16); \
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LOAD_MRF(m11, 0x14); \
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LOAD_MRF(m10, 0x12); \
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LOAD_MRF(m9, 0x10); \
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LOAD_MRF(m8, 0xe); \
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LOAD_MRF(m7, 0xc); \
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LOAD_MRF(m6, 0xa); \
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LOAD_MRF(m5, 0x8); \
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LOAD_MRF(m4, 0x6); \
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LOAD_MRF(m3, 0x4); \
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LOAD_MRF(m2, 0x2); \
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LOAD_MRF(m1, 0x0)
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#ifndef SANDYBRIDGE
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#error Only SandyBridge is supported
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#endif
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/* Default flags for an instruction */
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#define FLAGS { ALIGN1, SWITCH, MASK_DISABLE, ACCWRCTRL}
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/*
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* We can clobber m0, and g0.4, everything else must be saved.
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*/
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Enter:
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nop;
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or (1) cr0.0 cr0.0 CR0_0_ENTRY_UNMASK:ud FLAGS;
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/*
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* g0.5 has the per thread scratch space when running in FS or VS.
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* If we don't have a valid g0.5, we can calculate a per thread scratch offset
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* using the system registers. The problem is we do not have a good way to know
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* the offset from GSBA. The system routine will have to be hardcoded or
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* dynamically patched with the correct offset.
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* TID is in sr0.0[2:0]
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* EUID is in sr0.0[11:8]
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*/
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#ifdef GPGPU
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mov (1) g0.4:ud 0:ud FLAGS;
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#if 0
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/* This should work according to the docs, the add blows up */
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shr (1) g0.8:uw sr0.0:uw 5 FLAGS;
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add (1) g0.16:ub gr0.16:ub sr0.0:ub FLAGS;
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#else
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shr (1) g0.8:uw sr0.0:uw 5 FLAGS;
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mov (1) g0.9:uw sr0.0:uw FLAGS;
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and (1) g0.9:uw g0.9:uw 0x7:uw FLAGS;
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add (1) g0.8:uw g0.8:uw g0.9:uw FLAGS;
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mov (1) g0.9:uw 0:uw FLAGS;
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mul (1) g0.4:ud g0.4:ud PER_THREAD_QWORDS FLAGS;
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#endif
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#endif
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mov (8) m0:ud 0:ud FLAGS;
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/* Saves must occur in order so as not to clobber the next register */
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STORE_MRF(m0, 0);
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STORE_GRF(g0, 0x20);
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STORE_GRF(g1, 0x22);
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SAVE_ALL_MRF;
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mov (8) g1:ud STATE_EU_MSG:ud FLAGS;
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STORE_GRF(g1, STATE_QWORD);
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mov (8) g1:ud DEBUG_PROTOCOL_VERSION:ud FLAGS;
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STORE_GRF(g1, COMMUNICATION_QWORD);
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SAVE_CRF;
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EVICT_CACHE;
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wait n1:ud;
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EVICT_CACHE;
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/* Using this to try to keep coherency */
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LOAD_GRF(g1, CR_OFFSET);
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LOAD_GRF(g1, COMMUNICATION_QWORD);
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LOAD_GRF(g1, STATE_QWORD);
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RESTORE_ALL_MRF;
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LOAD_GRF(g1, 0x22);
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LOAD_GRF(g0, 0x20);
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/* Clear breakpoint status */
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and (1) cr0.1 cr0.1 CR0_1_ENTRY_UNMASK:ud FLAGS;
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/* set breakpoint suppress this should be conditional on bes */
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or (1) cr0.0 cr0.0 CR0_0_BP_SUPPRESS:ud FLAGS;
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and (1) cr0.0 cr0.0 CR0_0_RETURN_MASK:ud FLAGS;
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nop;
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