mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-07 16:06:25 +00:00
982f7eb238
This reveal that quite a few locations were writing relocation offsets but only allowing for 32 bit addresses. To reveal such places in active tests, we also now double check that we do not use more batch space than declared. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
368 lines
8.7 KiB
C
368 lines
8.7 KiB
C
#include <intel_bufmgr.h>
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#include <i915_drm.h>
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#include "media_fill.h"
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#include "gen8_media.h"
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#include "intel_reg.h"
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#include "drmtest.h"
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#include <assert.h>
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static const uint32_t media_kernel[][4] = {
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{ 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
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{ 0x00600001, 0x20800208, 0x008d0000, 0x00000000 },
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{ 0x00200001, 0x20800208, 0x00450040, 0x00000000 },
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{ 0x00000001, 0x20880608, 0x00000000, 0x000f000f },
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{ 0x00800001, 0x20a00208, 0x00000020, 0x00000000 },
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{ 0x00800001, 0x20e00208, 0x00000020, 0x00000000 },
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{ 0x00800001, 0x21200208, 0x00000020, 0x00000000 },
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{ 0x00800001, 0x21600208, 0x00000020, 0x00000000 },
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{ 0x0c800031, 0x24000a40, 0x0e000080, 0x120a8000 },
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{ 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
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{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
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};
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static uint32_t
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batch_used(struct intel_batchbuffer *batch)
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{
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return batch->ptr - batch->buffer;
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}
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static uint32_t
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batch_align(struct intel_batchbuffer *batch, uint32_t align)
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{
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uint32_t offset = batch_used(batch);
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offset = ALIGN(offset, align);
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batch->ptr = batch->buffer + offset;
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return offset;
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}
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static void *
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batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
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{
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uint32_t offset = batch_align(batch, align);
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batch->ptr += size;
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return memset(batch->buffer + offset, 0, size);
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}
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static uint32_t
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batch_offset(struct intel_batchbuffer *batch, void *ptr)
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{
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return (uint8_t *)ptr - batch->buffer;
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}
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static uint32_t
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batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
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{
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return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
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}
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static void
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gen8_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
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{
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int ret;
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ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
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if (ret == 0)
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ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
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NULL, 0, 0, 0);
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igt_assert(ret == 0);
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}
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static uint32_t
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gen8_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
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uint8_t color)
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{
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uint8_t *curbe_buffer;
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uint32_t offset;
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curbe_buffer = batch_alloc(batch, sizeof(uint32_t) * 8, 64);
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offset = batch_offset(batch, curbe_buffer);
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*curbe_buffer = color;
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return offset;
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}
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static uint32_t
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gen8_fill_surface_state(struct intel_batchbuffer *batch,
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struct igt_buf *buf,
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uint32_t format,
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int is_dst)
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{
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struct gen8_surface_state *ss;
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uint32_t write_domain, read_domain, offset;
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int ret;
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if (is_dst) {
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write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
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} else {
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write_domain = 0;
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read_domain = I915_GEM_DOMAIN_SAMPLER;
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}
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ss = batch_alloc(batch, sizeof(*ss), 64);
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offset = batch_offset(batch, ss);
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ss->ss0.surface_type = GEN8_SURFACE_2D;
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ss->ss0.surface_format = format;
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ss->ss0.render_cache_read_write = 1;
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ss->ss0.vertical_alignment = 1; /* align 4 */
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ss->ss0.horizontal_alignment = 1; /* align 4 */
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if (buf->tiling == I915_TILING_X)
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ss->ss0.tiled_mode = 2;
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else if (buf->tiling == I915_TILING_Y)
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ss->ss0.tiled_mode = 3;
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ss->ss8.base_addr = buf->bo->offset;
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ret = drm_intel_bo_emit_reloc(batch->bo,
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batch_offset(batch, ss) + 8 * 4,
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buf->bo, 0,
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read_domain, write_domain);
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igt_assert(ret == 0);
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ss->ss2.height = igt_buf_height(buf) - 1;
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ss->ss2.width = igt_buf_width(buf) - 1;
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ss->ss3.pitch = buf->stride - 1;
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ss->ss7.shader_chanel_select_r = 4;
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ss->ss7.shader_chanel_select_g = 5;
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ss->ss7.shader_chanel_select_b = 6;
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ss->ss7.shader_chanel_select_a = 7;
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return offset;
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}
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static uint32_t
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gen8_fill_binding_table(struct intel_batchbuffer *batch,
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struct igt_buf *dst)
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{
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uint32_t *binding_table, offset;
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binding_table = batch_alloc(batch, 32, 64);
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offset = batch_offset(batch, binding_table);
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binding_table[0] = gen8_fill_surface_state(batch, dst, GEN8_SURFACEFORMAT_R8_UNORM, 1);
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return offset;
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}
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static uint32_t
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gen8_fill_media_kernel(struct intel_batchbuffer *batch,
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const uint32_t kernel[][4],
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size_t size)
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{
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uint32_t offset;
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offset = batch_copy(batch, kernel, size, 64);
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return offset;
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}
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static uint32_t
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gen8_fill_interface_descriptor(struct intel_batchbuffer *batch, struct igt_buf *dst)
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{
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struct gen8_interface_descriptor_data *idd;
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uint32_t offset;
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uint32_t binding_table_offset, kernel_offset;
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binding_table_offset = gen8_fill_binding_table(batch, dst);
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kernel_offset = gen8_fill_media_kernel(batch, media_kernel, sizeof(media_kernel));
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idd = batch_alloc(batch, sizeof(*idd), 64);
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offset = batch_offset(batch, idd);
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idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
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idd->desc2.single_program_flow = 1;
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idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
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idd->desc3.sampler_count = 0; /* 0 samplers used */
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idd->desc3.sampler_state_pointer = 0;
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idd->desc4.binding_table_entry_count = 0;
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idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
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idd->desc5.constant_urb_entry_read_offset = 0;
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idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
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return offset;
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}
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static void
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gen8_emit_state_base_address(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2));
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/* general */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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/* stateless data port */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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/* surface */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
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/* dynamic */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
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0, BASE_ADDRESS_MODIFY);
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/* indirect */
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* instruction */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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/* general state buffer size */
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OUT_BATCH(0xfffff000 | 1);
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/* dynamic state buffer size */
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OUT_BATCH(1 << 12 | 1);
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/* indirect object buffer size */
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OUT_BATCH(0xfffff000 | 1);
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/* intruction buffer size, must set modify enable bit, otherwise it may result in GPU hang */
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OUT_BATCH(1 << 12 | 1);
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}
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static void
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gen8_emit_vfe_state(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN8_MEDIA_VFE_STATE | (9 - 2));
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/* scratch buffer */
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* number of threads & urb entries */
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OUT_BATCH(1 << 16 |
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2 << 8);
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OUT_BATCH(0);
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/* urb entry size & curbe size */
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OUT_BATCH(2 << 16 |
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2);
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/* scoreboard */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen8_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer)
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{
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OUT_BATCH(GEN8_MEDIA_CURBE_LOAD | (4 - 2));
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OUT_BATCH(0);
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/* curbe total data length */
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OUT_BATCH(64);
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/* curbe data start address, is relative to the dynamics base address */
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OUT_BATCH(curbe_buffer);
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}
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static void
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gen8_emit_interface_descriptor_load(struct intel_batchbuffer *batch, uint32_t interface_descriptor)
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{
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OUT_BATCH(GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
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OUT_BATCH(0);
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/* interface descriptor data length */
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OUT_BATCH(sizeof(struct gen8_interface_descriptor_data));
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/* interface descriptor address, is relative to the dynamics base address */
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OUT_BATCH(interface_descriptor);
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}
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static void
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gen8lp_emit_media_objects(struct intel_batchbuffer *batch,
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unsigned x, unsigned y,
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unsigned width, unsigned height)
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{
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int i, j;
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for (i = 0; i < width / 16; i++) {
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for (j = 0; j < height / 16; j++) {
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OUT_BATCH(GEN8_MEDIA_OBJECT | (8 - 2));
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/* interface descriptor offset */
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OUT_BATCH(0);
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/* without indirect data */
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* scoreboard */
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* inline data (xoffset, yoffset) */
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OUT_BATCH(x + i * 16);
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OUT_BATCH(y + j * 16);
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}
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}
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}
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/*
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* This sets up the media pipeline,
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*
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* +---------------+ <---- 4096
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* | ^ |
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* | | |
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* | various |
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* | state |
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* | | |
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* |_______|_______| <---- 2048 + ?
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* | ^ |
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* | | |
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* | batch |
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* | commands |
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* | | |
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* | | |
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* +---------------+ <---- 0 + ?
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*
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*/
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#define BATCH_STATE_SPLIT 2048
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void
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gen8lp_media_fillfunc(struct intel_batchbuffer *batch,
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struct igt_buf *dst,
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unsigned x, unsigned y,
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unsigned width, unsigned height,
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uint8_t color)
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{
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uint32_t curbe_buffer, interface_descriptor;
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uint32_t batch_end;
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intel_batchbuffer_flush(batch);
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/* setup states */
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batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
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curbe_buffer = gen8_fill_curbe_buffer_data(batch, color);
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interface_descriptor = gen8_fill_interface_descriptor(batch, dst);
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igt_assert(batch->ptr < &batch->buffer[4095]);
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/* media pipeline */
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batch->ptr = batch->buffer;
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OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
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gen8_emit_state_base_address(batch);
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gen8_emit_vfe_state(batch);
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gen8_emit_curbe_load(batch, curbe_buffer);
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gen8_emit_interface_descriptor_load(batch, interface_descriptor);
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gen8lp_emit_media_objects(batch, x, y, width, height);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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batch_end = batch_align(batch, 8);
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igt_assert(batch_end < BATCH_STATE_SPLIT);
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gen8_render_flush(batch, batch_end);
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intel_batchbuffer_reset(batch);
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}
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