Zhao Yakui
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88e5f1fdf8
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assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8
Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
>add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw
>add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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2013-11-06 09:39:41 -08:00 |
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Xiang, Haihao
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bf05bd5531
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assembler/bdw: Check & Refinement Engine message
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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2013-11-06 09:39:41 -08:00 |
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Xiang, Haihao
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b6a33bdcce
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assembler/bdw: Video Motion Estimation(VME) message
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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2013-11-06 09:39:41 -08:00 |
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Xiang, Haihao
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bf003ea634
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assembler/bdw: Thread Spawn message
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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2013-11-06 09:39:41 -08:00 |
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Xiang, Haihao
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01c9654a65
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assembler/bdw: Data port message
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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2013-11-06 09:39:41 -08:00 |
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Damien Lespiau
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c3b36592af
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assembler/bdw: Add gen8_instruction from mesa
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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2013-11-06 09:34:35 -08:00 |
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