The MOCS registers were added in Gen9 and define the caching policy.
The registers are split into two sets. The first set controls the
EDRAM policy and have a set for each engine, the second set controls
the L3 policy. The two sets use the same index.
The RCS registers and the L3CC registers are stored in the RCS context.
The test checks that the registers are correct by checking the values by
directly reading them via MMIO, then again it tests them by reading them
from within a batch buffer. RCS engine is tested last as it programs the
registers via a batch buffer and this will invalidate the test for
workloads that don't use the render ring or don't run a render batch
first.
v2: Reorganised the structure.
Added more tests. (Chris Wilson)
v3: Fixed a few bugs. (Chris Wilson)
v4: More Tidy-ups. (Chris Wilson)
SKL does does not have a snoop bit. (Peter Antoine)
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
