Aside from adding VEBOX support, this test allows allows the "mixed"
test case variant to work on platforms that have 2 rings which was
previously not the case. To the best of my memory, this might therefore
impact G45, and Ironlake.
Signed-off-by: Zhong Li <zhong.li@intel.com>
[Ben: added commit message, remove num_rings = 1, s/LOCACL/LOCAL]
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Using a dummy reloc that doesn't matter to trick the kernel into
synchroizing the rings.
v2: properly apply MI_NOOP workaround to MI_FLUSH_DW and
switch to MI_COND_BATCH_BUFFER_END as a dummy command on the
render ring to avoid PIPE_CONTROL errata.
v3: somebody clever decided that in C, you cound from 1,
i.e. I915_EXEC_RENDER == 1. It works now ...
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
