flywithu/ntel-gpu-tools
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2 Commits

Author SHA1 Message Date
Zhao Yakui
88e5f1fdf8 assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8 
Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
  >add.sat (16) r[a0.5,0]<1>:uw     r[a0.5,0]<16;16,1>:uw  0x0080:uw
  >add.sat (16) r[a0.5,32]<1>:uw    r[a0.5,32]<16;16,1>:uw 0x0080:uw

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-11-06 09:39:41 -08:00
Damien Lespiau
c3b36592af assembler/bdw: Add gen8_instruction from mesa 
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-11-06 09:34:35 -08:00