Zhao Yakui
8dc95202c8
assembler/skl: update the extdesc field for SEND instruction
...
The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate
for the extended message descriptors. And some bits of SEND instruction are defined
as the extdesc field.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30 12:21:03 +01:00
Zhao Yakui
88e5f1fdf8
assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8
...
Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
>add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw
>add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
bf05bd5531
assembler/bdw: Check & Refinement Engine message
...
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
b6a33bdcce
assembler/bdw: Video Motion Estimation(VME) message
...
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
bf003ea634
assembler/bdw: Thread Spawn message
...
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
01c9654a65
assembler/bdw: Data port message
...
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Damien Lespiau
c3b36592af
assembler/bdw: Add gen8_instruction from mesa
...
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
