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bdw: Update obvious missing blit support

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This provides a macro that allows us to update all the arbitrary blit
commands we have stuck throughout the code. It assumes we don't actually
use 64b relocs (which is currently true). This also allows us to easily find
all the areas we need to update later when we really use the upper dword.

This block was done mostly with a sed job, and represents the easier
in test blit implementations.

v2 by Oscar: s/OUT_BATCH/BEGIN_BATCH in BLIT_COPY_BATCH_START

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
This commit is contained in:
Ben Widawsky
2013-10-08 15:02:07 -07:00
parent 26f09a9189
commit f4dfa37e85
26 changed files with 107 additions and 114 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tests/gem_set_tiling_vs_blt.c
+9 -13
View File
@@ -85,19 +85,18 @@ static void do_test(uint32_t tiling, unsigned stride,
busy_bo = drm_intel_bo_alloc(bufmgr, "busy bo bo", 16*1024*1024, 4096);
for (i = 0; i < 250; i++) {
BEGIN_BATCH(8);
OUT_BATCH(XY_SRC_COPY_BLT_CMD |
XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB);
BLIT_COPY_BATCH_START(devid, 0);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
2*1024*4);
OUT_BATCH(0 << 16 | 1024);
OUT_BATCH((2048) << 16 | (2048));
OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
BLIT_RELOC_UDW(devid);
OUT_BATCH(0 << 16 | 0);
OUT_BATCH(2*1024*4);
OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
BLIT_RELOC_UDW(devid);
ADVANCE_BATCH();
if (IS_GEN6(devid) || IS_GEN7(devid)) {
@@ -158,20 +157,18 @@ static void do_test(uint32_t tiling, unsigned stride,
blt_bits = XY_SRC_COPY_BLT_SRC_TILED;
}
BEGIN_BATCH(8);
OUT_BATCH(XY_SRC_COPY_BLT_CMD |
XY_SRC_COPY_BLT_WRITE_ALPHA |
blt_bits |
XY_SRC_COPY_BLT_WRITE_RGB);
BLIT_COPY_BATCH_START(devid, blt_bits);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
stride);
OUT_BATCH(0 << 16 | 0);
OUT_BATCH((TEST_HEIGHT(stride)) << 16 | (TEST_WIDTH(stride)));
OUT_RELOC_FENCED(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
BLIT_RELOC_UDW(devid);
OUT_BATCH(0 << 16 | 0);
OUT_BATCH(blt_stride);
OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
BLIT_RELOC_UDW(devid);
ADVANCE_BATCH();
intel_batchbuffer_flush(batch);
@@ -186,19 +183,18 @@ static void do_test(uint32_t tiling, unsigned stride,
/* Note: We don't care about gen4+ here because the blitter doesn't use
* fences there. So not setting tiling flags on the tiled buffer is ok.
*/
BEGIN_BATCH(8);
OUT_BATCH(XY_SRC_COPY_BLT_CMD |
XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB);
BLIT_COPY_BATCH_START(devid, 0);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
stride_after);
OUT_BATCH(0 << 16 | 0);
OUT_BATCH((1) << 16 | (1));
OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
BLIT_RELOC_UDW(devid);
OUT_BATCH(0 << 16 | 0);
OUT_BATCH(stride_after);
OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
BLIT_RELOC_UDW(devid);
ADVANCE_BATCH();
intel_batchbuffer_flush(batch);